1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pwm/renesas,tpu-pwm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas R-Car Timer Pulse Unit PWM Controller 8 9maintainers: 10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 11 12select: 13 properties: 14 compatible: 15 contains: 16 const: renesas,tpu 17 required: 18 - compatible 19 - '#pwm-cells' 20 21properties: 22 compatible: 23 items: 24 - enum: 25 - renesas,tpu-r8a73a4 # R-Mobile APE6 26 - renesas,tpu-r8a7740 # R-Mobile A1 27 - renesas,tpu-r8a7742 # RZ/G1H 28 - renesas,tpu-r8a7743 # RZ/G1M 29 - renesas,tpu-r8a7744 # RZ/G1N 30 - renesas,tpu-r8a7745 # RZ/G1E 31 - renesas,tpu-r8a7790 # R-Car H2 32 - renesas,tpu-r8a7791 # R-Car M2-W 33 - renesas,tpu-r8a7792 # R-Car V2H 34 - renesas,tpu-r8a7793 # R-Car M2-N 35 - renesas,tpu-r8a7794 # R-Car E2 36 - renesas,tpu-r8a7795 # R-Car H3 37 - renesas,tpu-r8a7796 # R-Car M3-W 38 - renesas,tpu-r8a77965 # R-Car M3-N 39 - renesas,tpu-r8a77970 # R-Car V3M 40 - renesas,tpu-r8a77980 # R-Car V3H 41 - const: renesas,tpu 42 43 reg: 44 # Base address and length of each memory resource used by the PWM 45 # controller hardware module. 46 maxItems: 1 47 48 interrupts: 49 maxItems: 1 50 51 '#pwm-cells': 52 # should be 3. See pwm.yaml in this directory for a description of 53 # the cells format. The only third cell flag supported by this binding is 54 # PWM_POLARITY_INVERTED. 55 const: 3 56 57 clocks: 58 maxItems: 1 59 60 power-domains: 61 maxItems: 1 62 63 resets: 64 maxItems: 1 65 66required: 67 - compatible 68 - reg 69 - '#pwm-cells' 70 - clocks 71 - power-domains 72 73allOf: 74 - $ref: pwm.yaml# 75 76 - if: 77 not: 78 properties: 79 compatible: 80 contains: 81 enum: 82 - renesas,tpu-r8a73a4 83 - renesas,tpu-r8a7740 84 then: 85 required: 86 - resets 87 88additionalProperties: false 89 90examples: 91 - | 92 #include <dt-bindings/clock/r8a7740-clock.h> 93 94 tpu: pwm@e6600000 { 95 compatible = "renesas,tpu-r8a7740", "renesas,tpu"; 96 reg = <0xe6600000 0x148>; 97 clocks = <&mstp3_clks R8A7740_CLK_TPU0>; 98 power-domains = <&pd_a3sp>; 99 #pwm-cells = <3>; 100 }; 101