16b49329aSSagar Kadam# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
26b49329aSSagar Kadam# Copyright (C) 2020 SiFive, Inc.
36b49329aSSagar Kadam%YAML 1.2
46b49329aSSagar Kadam---
56b49329aSSagar Kadam$id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
66b49329aSSagar Kadam$schema: http://devicetree.org/meta-schemas/core.yaml#
76b49329aSSagar Kadam
86b49329aSSagar Kadamtitle: SiFive PWM controller
96b49329aSSagar Kadam
106b49329aSSagar Kadammaintainers:
116b49329aSSagar Kadam  - Yash Shah <yash.shah@sifive.com>
126b49329aSSagar Kadam  - Sagar Kadam <sagar.kadam@sifive.com>
136b49329aSSagar Kadam  - Paul Walmsley <paul.walmsley@sifive.com>
146b49329aSSagar Kadam
156b49329aSSagar Kadamdescription:
166b49329aSSagar Kadam  Unlike most other PWM controllers, the SiFive PWM controller currently
176b49329aSSagar Kadam  only supports one period for all channels in the PWM. All PWMs need to
186b49329aSSagar Kadam  run at the same period. The period also has significant restrictions on
196b49329aSSagar Kadam  the values it can achieve, which the driver rounds to the nearest
206b49329aSSagar Kadam  achievable period. PWM RTL that corresponds to the IP block version
216b49329aSSagar Kadam  numbers can be found here -
226b49329aSSagar Kadam
236b49329aSSagar Kadam  https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
246b49329aSSagar Kadam
25*e040921cSKrzysztof KozlowskiallOf:
26*e040921cSKrzysztof Kozlowski  - $ref: pwm.yaml#
27*e040921cSKrzysztof Kozlowski
286b49329aSSagar Kadamproperties:
296b49329aSSagar Kadam  compatible:
306b49329aSSagar Kadam    items:
31b1f592d5SYash Shah      - enum:
32b1f592d5SYash Shah          - sifive,fu540-c000-pwm
33b1f592d5SYash Shah          - sifive,fu740-c000-pwm
346b49329aSSagar Kadam      - const: sifive,pwm0
356b49329aSSagar Kadam    description:
366b49329aSSagar Kadam      Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
37b1f592d5SYash Shah      compatible strings are "sifive,fu540-c000-pwm" and
38b1f592d5SYash Shah      "sifive,fu740-c000-pwm" for the SiFive PWM v0 as integrated onto the
39b1f592d5SYash Shah      SiFive FU540 and FU740 chip respectively, and "sifive,pwm0" for the
406b49329aSSagar Kadam      SiFive PWM v0 IP block with no chip integration tweaks.
416b49329aSSagar Kadam      Please refer to sifive-blocks-ip-versioning.txt for details.
426b49329aSSagar Kadam
436b49329aSSagar Kadam  reg:
446b49329aSSagar Kadam    maxItems: 1
456b49329aSSagar Kadam
466b49329aSSagar Kadam  clocks:
476b49329aSSagar Kadam    maxItems: 1
486b49329aSSagar Kadam
496b49329aSSagar Kadam  "#pwm-cells":
506b49329aSSagar Kadam    const: 3
516b49329aSSagar Kadam
526b49329aSSagar Kadam  interrupts:
536b49329aSSagar Kadam    maxItems: 4
546b49329aSSagar Kadam    description:
556b49329aSSagar Kadam      Each PWM instance in FU540-C000 has 4 comparators. One interrupt per comparator.
566b49329aSSagar Kadam
576b49329aSSagar Kadamrequired:
586b49329aSSagar Kadam  - compatible
596b49329aSSagar Kadam  - reg
606b49329aSSagar Kadam  - clocks
616b49329aSSagar Kadam  - interrupts
626b49329aSSagar Kadam
636b49329aSSagar KadamadditionalProperties: false
646b49329aSSagar Kadam
656b49329aSSagar Kadamexamples:
666b49329aSSagar Kadam  - |
676b49329aSSagar Kadam    pwm:  pwm@10020000 {
686b49329aSSagar Kadam      compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
696b49329aSSagar Kadam      reg = <0x10020000 0x1000>;
706b49329aSSagar Kadam      clocks = <&tlclk>;
716b49329aSSagar Kadam      interrupt-parent = <&plic>;
726b49329aSSagar Kadam      interrupts = <42>, <43>, <44>, <45>;
736b49329aSSagar Kadam      #pwm-cells = <3>;
746b49329aSSagar Kadam    };
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