1b09b179bSXinlei Lee# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2b09b179bSXinlei Lee%YAML 1.2
3b09b179bSXinlei Lee---
4b09b179bSXinlei Lee$id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml#
5b09b179bSXinlei Lee$schema: http://devicetree.org/meta-schemas/core.yaml#
6b09b179bSXinlei Lee
7b09b179bSXinlei Leetitle: MediaTek DISP_PWM Controller Device Tree Bindings
8b09b179bSXinlei Lee
9b09b179bSXinlei Leemaintainers:
10b09b179bSXinlei Lee  - Jitao Shi <jitao.shi@mediatek.com>
11b09b179bSXinlei Lee  - Xinlei Lee <xinlei.lee@mediatek.com>
12b09b179bSXinlei Lee
13b09b179bSXinlei LeeallOf:
14b09b179bSXinlei Lee  - $ref: pwm.yaml#
15b09b179bSXinlei Lee
16b09b179bSXinlei Leeproperties:
17b09b179bSXinlei Lee  compatible:
18b09b179bSXinlei Lee    oneOf:
19b09b179bSXinlei Lee      - enum:
20b09b179bSXinlei Lee          - mediatek,mt2701-disp-pwm
21b09b179bSXinlei Lee          - mediatek,mt6595-disp-pwm
22b09b179bSXinlei Lee          - mediatek,mt8173-disp-pwm
23b09b179bSXinlei Lee          - mediatek,mt8183-disp-pwm
24b09b179bSXinlei Lee      - items:
25b09b179bSXinlei Lee          - const: mediatek,mt8167-disp-pwm
26b09b179bSXinlei Lee          - const: mediatek,mt8173-disp-pwm
27*b8ba2b42SXinlei Lee      - items:
28*b8ba2b42SXinlei Lee          - enum:
29*b8ba2b42SXinlei Lee              - mediatek,mt8192-disp-pwm
30*b8ba2b42SXinlei Lee          - const: mediatek,mt8183-disp-pwm
31b09b179bSXinlei Lee
32b09b179bSXinlei Lee  reg:
33b09b179bSXinlei Lee    maxItems: 1
34b09b179bSXinlei Lee
35b09b179bSXinlei Lee  "#pwm-cells":
36b09b179bSXinlei Lee    const: 2
37b09b179bSXinlei Lee
38b09b179bSXinlei Lee  clocks:
39b09b179bSXinlei Lee    items:
40b09b179bSXinlei Lee      - description: Main Clock
41b09b179bSXinlei Lee      - description: Mm Clock
42b09b179bSXinlei Lee
43b09b179bSXinlei Lee  clock-names:
44b09b179bSXinlei Lee    items:
45b09b179bSXinlei Lee      - const: main
46b09b179bSXinlei Lee      - const: mm
47b09b179bSXinlei Lee
48b09b179bSXinlei Leerequired:
49b09b179bSXinlei Lee  - compatible
50b09b179bSXinlei Lee  - reg
51b09b179bSXinlei Lee  - "#pwm-cells"
52b09b179bSXinlei Lee  - clocks
53b09b179bSXinlei Lee  - clock-names
54b09b179bSXinlei Lee
55b09b179bSXinlei LeeadditionalProperties: false
56b09b179bSXinlei Lee
57b09b179bSXinlei Leeexamples:
58b09b179bSXinlei Lee  - |
59b09b179bSXinlei Lee    #include <dt-bindings/interrupt-controller/arm-gic.h>
60b09b179bSXinlei Lee    #include <dt-bindings/clock/mt8173-clk.h>
61b09b179bSXinlei Lee    #include <dt-bindings/interrupt-controller/irq.h>
62b09b179bSXinlei Lee
63b09b179bSXinlei Lee    pwm0: pwm@1401e000 {
64b09b179bSXinlei Lee        compatible = "mediatek,mt8173-disp-pwm";
65b09b179bSXinlei Lee        reg = <0x1401e000 0x1000>;
66b09b179bSXinlei Lee        #pwm-cells = <2>;
67b09b179bSXinlei Lee        clocks = <&mmsys CLK_MM_DISP_PWM026M>,
68b09b179bSXinlei Lee                 <&mmsys CLK_MM_DISP_PWM0MM>;
69b09b179bSXinlei Lee        clock-names = "main", "mm";
70b09b179bSXinlei Lee    };
71