1* Freescale QorIQ 1588 timer based PTP clock
2
3General Properties:
4
5  - compatible   Should be "fsl,etsec-ptp" for eTSEC
6                 Should be "fsl,fman-ptp-timer" for DPAA FMan
7  - reg          Offset and length of the register set for the device
8  - interrupts   There should be at least two interrupts. Some devices
9                 have as many as four PTP related interrupts.
10
11Clock Properties:
12
13  - fsl,cksel        Timer reference clock source.
14  - fsl,tclk-period  Timer reference clock period in nanoseconds.
15  - fsl,tmr-prsc     Prescaler, divides the output clock.
16  - fsl,tmr-add      Frequency compensation value.
17  - fsl,tmr-fiper1   Fixed interval period pulse generator.
18  - fsl,tmr-fiper2   Fixed interval period pulse generator.
19  - fsl,max-adj      Maximum frequency adjustment in parts per billion.
20  - fsl,extts-fifo   The presence of this property indicates hardware
21		     support for the external trigger stamp FIFO.
22  - little-endian    The presence of this property indicates the 1588 timer
23		     IP block is little-endian mode. The default endian mode
24		     is big-endian.
25
26  These properties set the operational parameters for the PTP
27  clock. You must choose these carefully for the clock to work right.
28  Here is how to figure good values:
29
30  TimerOsc     = selected reference clock   MHz
31  tclk_period  = desired clock period       nanoseconds
32  NominalFreq  = 1000 / tclk_period         MHz
33  FreqDivRatio = TimerOsc / NominalFreq     (must be greater that 1.0)
34  tmr_add      = ceil(2^32 / FreqDivRatio)
35  OutputClock  = NominalFreq / tmr_prsc     MHz
36  PulseWidth   = 1 / OutputClock            microseconds
37  FiperFreq1   = desired frequency in Hz
38  FiperDiv1    = 1000000 * OutputClock / FiperFreq1
39  tmr_fiper1   = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
40  max_adj      = 1000000000 * (FreqDivRatio - 1.0) - 1
41
42  The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
43  driver expects that tmr_fiper1 will be correctly set to produce a 1
44  Pulse Per Second (PPS) signal, since this will be offered to the PPS
45  subsystem to synchronize the Linux clock.
46
47  Reference clock source is determined by the value, which is holded
48  in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
49  value, which will be directly written in those bits, that is why,
50  according to reference manual, the next clock sources can be used:
51
52  For eTSEC,
53  <0> - external high precision timer reference clock (TSEC_TMR_CLK
54        input is used for this purpose);
55  <1> - eTSEC system clock;
56  <2> - eTSEC1 transmit clock;
57  <3> - RTC clock input.
58
59  For DPAA FMan,
60  <0> - external high precision timer reference clock (TMR_1588_CLK)
61  <1> - MAC system clock (1/2 FMan clock)
62  <2> - reserved
63  <3> - RTC clock oscillator
64
65  When this attribute is not used, the IEEE 1588 timer reference clock
66  will use the eTSEC system clock (for Gianfar) or the MAC system
67  clock (for DPAA).
68
69Example:
70
71	ptp_clock@24e00 {
72		compatible = "fsl,etsec-ptp";
73		reg = <0x24E00 0xB0>;
74		interrupts = <12 0x8 13 0x8>;
75		interrupt-parent = < &ipic >;
76		fsl,cksel       = <1>;
77		fsl,tclk-period = <10>;
78		fsl,tmr-prsc    = <100>;
79		fsl,tmr-add     = <0x999999A4>;
80		fsl,tmr-fiper1  = <0x3B9AC9F6>;
81		fsl,tmr-fiper2  = <0x00018696>;
82		fsl,max-adj     = <659999998>;
83	};
84