1=====================================================================
2Freescale MPIC Interrupt Controller Node
3Copyright (C) 2010,2011 Freescale Semiconductor Inc.
4=====================================================================
5
6The Freescale MPIC interrupt controller is found on all PowerQUICC
7and QorIQ processors and is compatible with the Open PIC.  The
8notable difference from Open PIC binding is the addition of 2
9additional cells in the interrupt specifier defining interrupt type
10information.
11
12PROPERTIES
13
14  - compatible
15      Usage: required
16      Value type: <string>
17      Definition: Shall include "fsl,mpic".  Freescale MPIC
18          controllers compatible with this binding have Block
19          Revision Registers BRR1 and BRR2 at offset 0x0 and
20          0x10 in the MPIC.
21
22  - reg
23      Usage: required
24      Value type: <prop-encoded-array>
25      Definition: A standard property.  Specifies the physical
26          offset and length of the device's registers within the
27          CCSR address space.
28
29  - interrupt-controller
30      Usage: required
31      Value type: <empty>
32      Definition: Specifies that this node is an interrupt
33          controller
34
35  - #interrupt-cells
36      Usage: required
37      Value type: <u32>
38      Definition: Shall be 2 or 4.  A value of 2 means that interrupt
39          specifiers do not contain the interrupt-type or type-specific
40          information cells.
41
42  - #address-cells
43      Usage: required
44      Value type: <u32>
45      Definition: Shall be 0.
46
47  - pic-no-reset
48      Usage: optional
49      Value type: <empty>
50      Definition: The presence of this property specifies that the
51          MPIC must not be reset by the client program, and that
52          the boot program has initialized all interrupt source
53          configuration registers to a sane state-- masked or
54          directed at other cores.  This ensures that the client
55          program will not receive interrupts for sources not belonging
56          to the client.  The presence of this property also mandates
57          that any initialization related to interrupt sources shall
58          be limited to sources explicitly referenced in the device tree.
59
60  - big-endian
61      Usage: optional
62      Value type: <empty>
63          If present the MPIC will be assumed to be big-endian.  Some
64          device-trees omit this property on MPIC nodes even when the MPIC is
65          in fact big-endian, so certain boards override this property.
66
67INTERRUPT SPECIFIER DEFINITION
68
69  Interrupt specifiers consists of 4 cells encoded as
70  follows:
71
72   <1st-cell>   interrupt-number
73
74                Identifies the interrupt source.  The meaning
75                depends on the type of interrupt.
76
77                Note: If the interrupt-type cell is undefined
78                (i.e. #interrupt-cells = 2), this cell
79                should be interpreted the same as for
80                interrupt-type 0-- i.e. an external or
81                normal SoC device interrupt.
82
83   <2nd-cell>   level-sense information, encoded as follows:
84                    0 = low-to-high edge triggered
85                    1 = active low level-sensitive
86                    2 = active high level-sensitive
87                    3 = high-to-low edge triggered
88
89   <3rd-cell>   interrupt-type
90
91                The following types are supported:
92
93                  0 = external or normal SoC device interrupt
94
95                      The interrupt-number cell contains
96                      the SoC device interrupt number.  The
97                      type-specific cell is undefined.  The
98                      interrupt-number is derived from the
99                      MPIC a block of registers referred to as
100                      the "Interrupt Source Configuration Registers".
101                      Each source has 32-bytes of registers
102                      (vector/priority and destination) in this
103                      region.   So interrupt 0 is at offset 0x0,
104                      interrupt 1 is at offset 0x20, and so on.
105
106                  1 = error interrupt
107
108                      The interrupt-number cell contains
109                      the SoC device interrupt number for
110                      the error interrupt.  The type-specific
111                      cell identifies the specific error
112                      interrupt number.
113
114                  2 = MPIC inter-processor interrupt (IPI)
115
116                      The interrupt-number cell identifies
117                      the MPIC IPI number.  The type-specific
118                      cell is undefined.
119
120                  3 = MPIC timer interrupt
121
122                      The interrupt-number cell identifies
123                      the MPIC timer number.  The type-specific
124                      cell is undefined.
125
126   <4th-cell>   type-specific information
127
128                The type-specific cell is encoded as follows:
129
130                 - For interrupt-type 1 (error interrupt),
131                   the type-specific cell contains the
132                   bit number of the error interrupt in the
133                   Error Interrupt Summary Register.
134
135EXAMPLE 1
136	/*
137	 * mpic interrupt controller with 4 cells per specifier
138	 */
139	mpic: pic@40000 {
140		compatible = "fsl,mpic";
141		interrupt-controller;
142		#interrupt-cells = <4>;
143		#address-cells = <0>;
144		reg = <0x40000 0x40000>;
145	};
146
147EXAMPLE 2
148	/*
149	 * The MPC8544 I2C controller node has an internal
150	 * interrupt number of 27.  As per the reference manual
151	 * this corresponds to interrupt source configuration
152	 * registers at 0x5_0560.
153	 *
154	 * The interrupt source configuration registers begin
155	 * at 0x5_0000.
156	 *
157	 * To compute the interrupt specifier interrupt number
158         *
159	 *       0x560 >> 5 = 43
160	 *
161	 * The interrupt source configuration registers begin
162	 * at 0x5_0000, and so the i2c vector/priority registers
163	 * are at 0x5_0560.
164	 */
165	i2c@3000 {
166		#address-cells = <1>;
167		#size-cells = <0>;
168		cell-index = <0>;
169		compatible = "fsl-i2c";
170		reg = <0x3000 0x100>;
171		interrupts = <43 2>;
172		interrupt-parent = <&mpic>;
173		dfsrr;
174	};
175
176
177EXAMPLE 3
178	/*
179	 *  Definition of a node defining the 4
180	 *  MPIC IPI interrupts.  Note the interrupt
181	 *  type of 2.
182	 */
183	ipi@410a0 {
184		compatible = "fsl,mpic-ipi";
185		reg = <0x40040 0x10>;
186		interrupts = <0 0 2 0
187		              1 0 2 0
188		              2 0 2 0
189		              3 0 2 0>;
190	};
191
192EXAMPLE 4
193	/*
194	 *  Definition of a node defining the MPIC
195	 *  global timers.  Note the interrupt
196	 *  type of 3.
197	 */
198	timer0: timer@41100 {
199		compatible = "fsl,mpic-global-timer";
200		reg = <0x41100 0x100 0x41300 4>;
201		interrupts = <0 0 3 0
202		              1 0 3 0
203		              2 0 3 0
204		              3 0 3 0>;
205	};
206
207EXAMPLE 5
208	/*
209	 * Definition of an error interrupt (interrupt type 1).
210	 * SoC interrupt number is 16 and the specific error
211         * interrupt bit in the error interrupt summary register
212	 * is 23.
213	 */
214	memory-controller@8000 {
215		compatible = "fsl,p4080-memory-controller";
216		reg = <0x8000 0x1000>;
217		interrupts = <16 2 1 23>;
218	};
219