1=====================================================================
2Freescale MPIC Interrupt Controller Node
3Copyright (C) 2010,2011 Freescale Semiconductor Inc.
4=====================================================================
5
6The Freescale MPIC interrupt controller is found on all PowerQUICC
7and QorIQ processors and is compatible with the Open PIC.  The
8notable difference from Open PIC binding is the addition of 2
9additional cells in the interrupt specifier defining interrupt type
10information.
11
12PROPERTIES
13
14  - compatible
15      Usage: required
16      Value type: <string>
17      Definition: Shall include "fsl,mpic".  Freescale MPIC
18          controllers compatible with this binding have Block
19          Revision Registers BRR1 and BRR2 at offset 0x0 and
20          0x10 in the MPIC.
21
22  - reg
23      Usage: required
24      Value type: <prop-encoded-array>
25      Definition: A standard property.  Specifies the physical
26          offset and length of the device's registers within the
27          CCSR address space.
28
29  - interrupt-controller
30      Usage: required
31      Value type: <empty>
32      Definition: Specifies that this node is an interrupt
33          controller
34
35  - #interrupt-cells
36      Usage: required
37      Value type: <u32>
38      Definition: Shall be 2 or 4.  A value of 2 means that interrupt
39          specifiers do not contain the interrupt-type or type-specific
40          information cells.
41
42  - #address-cells
43      Usage: required
44      Value type: <u32>
45      Definition: Shall be 0.
46
47  - pic-no-reset
48      Usage: optional
49      Value type: <empty>
50      Definition: The presence of this property specifies that the
51          MPIC must not be reset by the client program, and that
52          the boot program has initialized all interrupt source
53          configuration registers to a sane state-- masked or
54          directed at other cores.  This ensures that the client
55          program will not receive interrupts for sources not belonging
56          to the client.  The presence of this property also mandates
57          that any initialization related to interrupt sources shall
58          be limited to sources explicitly referenced in the device tree.
59
60INTERRUPT SPECIFIER DEFINITION
61
62  Interrupt specifiers consists of 4 cells encoded as
63  follows:
64
65   <1st-cell>   interrupt-number
66
67                Identifies the interrupt source.  The meaning
68                depends on the type of interrupt.
69
70                Note: If the interrupt-type cell is undefined
71                (i.e. #interrupt-cells = 2), this cell
72                should be interpreted the same as for
73                interrupt-type 0-- i.e. an external or
74                normal SoC device interrupt.
75
76   <2nd-cell>   level-sense information, encoded as follows:
77                    0 = low-to-high edge triggered
78                    1 = active low level-sensitive
79                    2 = active high level-sensitive
80                    3 = high-to-low edge triggered
81
82   <3rd-cell>   interrupt-type
83
84                The following types are supported:
85
86                  0 = external or normal SoC device interrupt
87
88                      The interrupt-number cell contains
89                      the SoC device interrupt number.  The
90                      type-specific cell is undefined.  The
91                      interrupt-number is derived from the
92                      MPIC a block of registers referred to as
93                      the "Interrupt Source Configuration Registers".
94                      Each source has 32-bytes of registers
95                      (vector/priority and destination) in this
96                      region.   So interrupt 0 is at offset 0x0,
97                      interrupt 1 is at offset 0x20, and so on.
98
99                  1 = error interrupt
100
101                      The interrupt-number cell contains
102                      the SoC device interrupt number for
103                      the error interrupt.  The type-specific
104                      cell identifies the specific error
105                      interrupt number.
106
107                  2 = MPIC inter-processor interrupt (IPI)
108
109                      The interrupt-number cell identifies
110                      the MPIC IPI number.  The type-specific
111                      cell is undefined.
112
113                  3 = MPIC timer interrupt
114
115                      The interrupt-number cell identifies
116                      the MPIC timer number.  The type-specific
117                      cell is undefined.
118
119   <4th-cell>   type-specific information
120
121                The type-specific cell is encoded as follows:
122
123                 - For interrupt-type 1 (error interrupt),
124                   the type-specific cell contains the
125                   bit number of the error interrupt in the
126                   Error Interrupt Summary Register.
127
128EXAMPLE 1
129	/*
130	 * mpic interrupt controller with 4 cells per specifier
131	 */
132	mpic: pic@40000 {
133		compatible = "fsl,mpic";
134		interrupt-controller;
135		#interrupt-cells = <4>;
136		#address-cells = <0>;
137		reg = <0x40000 0x40000>;
138	};
139
140EXAMPLE 2
141	/*
142	 * The MPC8544 I2C controller node has an internal
143	 * interrupt number of 27.  As per the reference manual
144	 * this corresponds to interrupt source configuration
145	 * registers at 0x5_0560.
146	 *
147	 * The interrupt source configuration registers begin
148	 * at 0x5_0000.
149	 *
150	 * To compute the interrupt specifier interrupt number
151         *
152	 *       0x560 >> 5 = 43
153	 *
154	 * The interrupt source configuration registers begin
155	 * at 0x5_0000, and so the i2c vector/priority registers
156	 * are at 0x5_0560.
157	 */
158	i2c@3000 {
159		#address-cells = <1>;
160		#size-cells = <0>;
161		cell-index = <0>;
162		compatible = "fsl-i2c";
163		reg = <0x3000 0x100>;
164		interrupts = <43 2>;
165		interrupt-parent = <&mpic>;
166		dfsrr;
167	};
168
169
170EXAMPLE 3
171	/*
172	 *  Definition of a node defining the 4
173	 *  MPIC IPI interrupts.  Note the interrupt
174	 *  type of 2.
175	 */
176	ipi@410a0 {
177		compatible = "fsl,mpic-ipi";
178		reg = <0x40040 0x10>;
179		interrupts = <0 0 2 0
180		              1 0 2 0
181		              2 0 2 0
182		              3 0 2 0>;
183	};
184
185EXAMPLE 4
186	/*
187	 *  Definition of a node defining the MPIC
188	 *  global timers.  Note the interrupt
189	 *  type of 3.
190	 */
191	timer0: timer@41100 {
192		compatible = "fsl,mpic-global-timer";
193		reg = <0x41100 0x100 0x41300 4>;
194		interrupts = <0 0 3 0
195		              1 0 3 0
196		              2 0 3 0
197		              3 0 3 0>;
198	};
199
200EXAMPLE 5
201	/*
202	 * Definition of an error interrupt (interrupt type 1).
203	 * SoC interrupt number is 16 and the specific error
204         * interrupt bit in the error interrupt summary register
205	 * is 23.
206	 */
207	memory-controller@8000 {
208		compatible = "fsl,p4080-memory-controller";
209		reg = <0x8000 0x1000>;
210		interrupts = <16 2 1 23>;
211	};
212