1d524dac9SGrant LikelyMPC5121 PSC Device Tree Bindings 2d524dac9SGrant Likely 3d524dac9SGrant LikelyPSC in UART mode 4d524dac9SGrant Likely---------------- 5d524dac9SGrant Likely 6d524dac9SGrant LikelyFor PSC in UART mode the needed PSC serial devices 7d524dac9SGrant Likelyare specified by fsl,mpc5121-psc-uart nodes in the 8d524dac9SGrant Likelyfsl,mpc5121-immr SoC node. Additionally the PSC FIFO 9d524dac9SGrant LikelyController node fsl,mpc5121-psc-fifo is requered there: 10d524dac9SGrant Likely 11d524dac9SGrant Likelyfsl,mpc5121-psc-uart nodes 12d524dac9SGrant Likely-------------------------- 13d524dac9SGrant Likely 14d524dac9SGrant LikelyRequired properties : 15d524dac9SGrant Likely - compatible : Should contain "fsl,mpc5121-psc-uart" and "fsl,mpc5121-psc" 16d524dac9SGrant Likely - cell-index : Index of the PSC in hardware 17d524dac9SGrant Likely - reg : Offset and length of the register set for the PSC device 18d524dac9SGrant Likely - interrupts : <a b> where a is the interrupt number of the 19d524dac9SGrant Likely PSC FIFO Controller and b is a field that represents an 20d524dac9SGrant Likely encoding of the sense and level information for the interrupt. 21d524dac9SGrant Likely - interrupt-parent : the phandle for the interrupt controller that 22d524dac9SGrant Likely services interrupts for this device. 23d524dac9SGrant Likely 24d524dac9SGrant LikelyRecommended properties : 25d524dac9SGrant Likely - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4) 26d524dac9SGrant Likely - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4) 27d524dac9SGrant Likely 28d524dac9SGrant Likely 29d524dac9SGrant Likelyfsl,mpc5121-psc-fifo node 30d524dac9SGrant Likely------------------------- 31d524dac9SGrant Likely 32d524dac9SGrant LikelyRequired properties : 33d524dac9SGrant Likely - compatible : Should be "fsl,mpc5121-psc-fifo" 34d524dac9SGrant Likely - reg : Offset and length of the register set for the PSC 35d524dac9SGrant Likely FIFO Controller 36d524dac9SGrant Likely - interrupts : <a b> where a is the interrupt number of the 37d524dac9SGrant Likely PSC FIFO Controller and b is a field that represents an 38d524dac9SGrant Likely encoding of the sense and level information for the interrupt. 39d524dac9SGrant Likely - interrupt-parent : the phandle for the interrupt controller that 40d524dac9SGrant Likely services interrupts for this device. 41d524dac9SGrant Likely 42d524dac9SGrant Likely 43d524dac9SGrant LikelyExample for a board using PSC0 and PSC1 devices in serial mode: 44d524dac9SGrant Likely 45d524dac9SGrant Likelyserial@11000 { 46d524dac9SGrant Likely compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 47d524dac9SGrant Likely cell-index = <0>; 48d524dac9SGrant Likely reg = <0x11000 0x100>; 49d524dac9SGrant Likely interrupts = <40 0x8>; 50d524dac9SGrant Likely interrupt-parent = < &ipic >; 51d524dac9SGrant Likely fsl,rx-fifo-size = <16>; 52d524dac9SGrant Likely fsl,tx-fifo-size = <16>; 53d524dac9SGrant Likely}; 54d524dac9SGrant Likely 55d524dac9SGrant Likelyserial@11100 { 56d524dac9SGrant Likely compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 57d524dac9SGrant Likely cell-index = <1>; 58d524dac9SGrant Likely reg = <0x11100 0x100>; 59d524dac9SGrant Likely interrupts = <40 0x8>; 60d524dac9SGrant Likely interrupt-parent = < &ipic >; 61d524dac9SGrant Likely fsl,rx-fifo-size = <16>; 62d524dac9SGrant Likely fsl,tx-fifo-size = <16>; 63d524dac9SGrant Likely}; 64d524dac9SGrant Likely 65d524dac9SGrant Likelypscfifo@11f00 { 66d524dac9SGrant Likely compatible = "fsl,mpc5121-psc-fifo"; 67d524dac9SGrant Likely reg = <0x11f00 0x100>; 68d524dac9SGrant Likely interrupts = <40 0x8>; 69d524dac9SGrant Likely interrupt-parent = < &ipic >; 70d524dac9SGrant Likely}; 71