1===================================================================
2Power Architecture CPU Binding
3Copyright 2013 Freescale Semiconductor Inc.
4
5Power Architecture CPUs in Freescale SOCs are represented in device trees as
6per the definition in ePAPR.
7
8In addition to the ePAPR definitions, the properties defined below may be
9present on CPU nodes.
10
11PROPERTIES
12
13   - fsl,eref-*
14        Usage: optional
15        Value type: <empty>
16        Definition: The EREF (EREF: A Programmer.s Reference Manual for
17	Freescale Power Architecture) defines the architecture for Freescale
18	Power CPUs.  The EREF defines some architecture categories not defined
19	by the Power ISA.  For these EREF-specific categories, the existence of
20	a property named fsl,eref-[CAT], where [CAT] is the abbreviated category
21	name with all uppercase letters converted to lowercase, indicates that
22	the category is supported by the implementation.
23