1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek Power Domains Controller
8
9maintainers:
10  - Weiyi Lu <weiyi.lu@mediatek.com>
11  - Matthias Brugger <mbrugger@suse.com>
12
13description: |
14  Mediatek processors include support for multiple power domains which can be
15  powered up/down by software based on different application scenes to save power.
16
17  IP cores belonging to a power domain should contain a 'power-domains'
18  property that is a phandle for SCPSYS node representing the domain.
19
20properties:
21  $nodename:
22    const: power-controller
23
24  compatible:
25    enum:
26      - mediatek,mt8173-power-controller
27      - mediatek,mt8183-power-controller
28      - mediatek,mt8192-power-controller
29
30  '#power-domain-cells':
31    const: 1
32
33  '#address-cells':
34    const: 1
35
36  '#size-cells':
37    const: 0
38
39patternProperties:
40  "^power-domain@[0-9a-f]+$":
41    type: object
42    description: |
43      Represents the power domains within the power controller node as documented
44      in Documentation/devicetree/bindings/power/power-domain.yaml.
45
46    properties:
47
48      '#power-domain-cells':
49        description:
50          Must be 0 for nodes representing a single PM domain and 1 for nodes
51          providing multiple PM domains.
52
53      '#address-cells':
54        const: 1
55
56      '#size-cells':
57        const: 0
58
59      reg:
60        description: |
61          Power domain index. Valid values are defined in:
62              "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
63              "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
64              "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
65        maxItems: 1
66
67      clocks:
68        description: |
69          A number of phandles to clocks that need to be enabled during domain
70          power-up sequencing.
71
72      clock-names:
73        description: |
74          List of names of clocks, in order to match the power-up sequencing
75          for each power domain we need to group the clocks by name. BASIC
76          clocks need to be enabled before enabling the corresponding power
77          domain, and should not have a '-' in their name (i.e mm, mfg, venc).
78          SUSBYS clocks need to be enabled before releasing the bus protection,
79          and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
80
81          In order to follow properly the power-up sequencing, the clocks must
82          be specified by order, adding first the BASIC clocks followed by the
83          SUSBSYS clocks.
84
85      mediatek,infracfg:
86        $ref: /schemas/types.yaml#/definitions/phandle
87        description: phandle to the device containing the INFRACFG register range.
88
89      mediatek,smi:
90        $ref: /schemas/types.yaml#/definitions/phandle
91        description: phandle to the device containing the SMI register range.
92
93    patternProperties:
94      "^power-domain@[0-9a-f]+$":
95        type: object
96        description: |
97          Represents a power domain child within a power domain parent node.
98
99        properties:
100
101          '#power-domain-cells':
102            description:
103              Must be 0 for nodes representing a single PM domain and 1 for nodes
104              providing multiple PM domains.
105
106          '#address-cells':
107            const: 1
108
109          '#size-cells':
110            const: 0
111
112          reg:
113            maxItems: 1
114
115          clocks:
116            description: |
117              A number of phandles to clocks that need to be enabled during domain
118              power-up sequencing.
119
120          clock-names:
121            description: |
122              List of names of clocks, in order to match the power-up sequencing
123              for each power domain we need to group the clocks by name. BASIC
124              clocks need to be enabled before enabling the corresponding power
125              domain, and should not have a '-' in their name (i.e mm, mfg, venc).
126              SUSBYS clocks need to be enabled before releasing the bus protection,
127              and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
128
129              In order to follow properly the power-up sequencing, the clocks must
130              be specified by order, adding first the BASIC clocks followed by the
131              SUSBSYS clocks.
132
133          mediatek,infracfg:
134            $ref: /schemas/types.yaml#/definitions/phandle
135            description: phandle to the device containing the INFRACFG register range.
136
137          mediatek,smi:
138            $ref: /schemas/types.yaml#/definitions/phandle
139            description: phandle to the device containing the SMI register range.
140
141        patternProperties:
142          "^power-domain@[0-9a-f]+$":
143            type: object
144            description: |
145              Represents a power domain child within a power domain parent node.
146
147            properties:
148
149              '#power-domain-cells':
150                description:
151                  Must be 0 for nodes representing a single PM domain and 1 for nodes
152                  providing multiple PM domains.
153
154              '#address-cells':
155                const: 1
156
157              '#size-cells':
158                const: 0
159
160              reg:
161                maxItems: 1
162
163              clocks:
164                description: |
165                  A number of phandles to clocks that need to be enabled during domain
166                  power-up sequencing.
167
168              clock-names:
169                description: |
170                  List of names of clocks, in order to match the power-up sequencing
171                  for each power domain we need to group the clocks by name. BASIC
172                  clocks need to be enabled before enabling the corresponding power
173                  domain, and should not have a '-' in their name (i.e mm, mfg, venc).
174                  SUSBYS clocks need to be enabled before releasing the bus protection,
175                  and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
176
177                  In order to follow properly the power-up sequencing, the clocks must
178                  be specified by order, adding first the BASIC clocks followed by the
179                  SUSBSYS clocks.
180
181              mediatek,infracfg:
182                $ref: /schemas/types.yaml#/definitions/phandle
183                description: phandle to the device containing the INFRACFG register range.
184
185              mediatek,smi:
186                $ref: /schemas/types.yaml#/definitions/phandle
187                description: phandle to the device containing the SMI register range.
188
189            required:
190              - reg
191
192            additionalProperties: false
193
194        required:
195          - reg
196
197        additionalProperties: false
198
199    required:
200      - reg
201
202    additionalProperties: false
203
204required:
205  - compatible
206
207additionalProperties: false
208
209examples:
210  - |
211    #include <dt-bindings/clock/mt8173-clk.h>
212    #include <dt-bindings/power/mt8173-power.h>
213
214    soc {
215        #address-cells = <2>;
216        #size-cells = <2>;
217
218        scpsys: syscon@10006000 {
219            compatible = "syscon", "simple-mfd";
220            reg = <0 0x10006000 0 0x1000>;
221
222            spm: power-controller {
223                compatible = "mediatek,mt8173-power-controller";
224                #address-cells = <1>;
225                #size-cells = <0>;
226                #power-domain-cells = <1>;
227
228                /* power domains of the SoC */
229                power-domain@MT8173_POWER_DOMAIN_VDEC {
230                    reg = <MT8173_POWER_DOMAIN_VDEC>;
231                    clocks = <&topckgen CLK_TOP_MM_SEL>;
232                    clock-names = "mm";
233                    #power-domain-cells = <0>;
234                };
235                power-domain@MT8173_POWER_DOMAIN_VENC {
236                    reg = <MT8173_POWER_DOMAIN_VENC>;
237                    clocks = <&topckgen CLK_TOP_MM_SEL>,
238                             <&topckgen CLK_TOP_VENC_SEL>;
239                    clock-names = "mm", "venc";
240                    #power-domain-cells = <0>;
241                };
242                power-domain@MT8173_POWER_DOMAIN_ISP {
243                    reg = <MT8173_POWER_DOMAIN_ISP>;
244                    clocks = <&topckgen CLK_TOP_MM_SEL>;
245                    clock-names = "mm";
246                    #power-domain-cells = <0>;
247                };
248                power-domain@MT8173_POWER_DOMAIN_MM {
249                    reg = <MT8173_POWER_DOMAIN_MM>;
250                    clocks = <&topckgen CLK_TOP_MM_SEL>;
251                    clock-names = "mm";
252                    #power-domain-cells = <0>;
253                    mediatek,infracfg = <&infracfg>;
254                };
255                power-domain@MT8173_POWER_DOMAIN_VENC_LT {
256                    reg = <MT8173_POWER_DOMAIN_VENC_LT>;
257                    clocks = <&topckgen CLK_TOP_MM_SEL>,
258                             <&topckgen CLK_TOP_VENC_LT_SEL>;
259                    clock-names = "mm", "venclt";
260                    #power-domain-cells = <0>;
261                };
262                power-domain@MT8173_POWER_DOMAIN_AUDIO {
263                    reg = <MT8173_POWER_DOMAIN_AUDIO>;
264                    #power-domain-cells = <0>;
265                };
266                power-domain@MT8173_POWER_DOMAIN_USB {
267                    reg = <MT8173_POWER_DOMAIN_USB>;
268                    #power-domain-cells = <0>;
269                };
270                power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
271                    reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
272                    clocks = <&clk26m>;
273                    clock-names = "mfg";
274                    #address-cells = <1>;
275                    #size-cells = <0>;
276                    #power-domain-cells = <1>;
277
278                    power-domain@MT8173_POWER_DOMAIN_MFG_2D {
279                        reg = <MT8173_POWER_DOMAIN_MFG_2D>;
280                        #address-cells = <1>;
281                        #size-cells = <0>;
282                        #power-domain-cells = <1>;
283
284                        power-domain@MT8173_POWER_DOMAIN_MFG {
285                            reg = <MT8173_POWER_DOMAIN_MFG>;
286                            #power-domain-cells = <0>;
287                            mediatek,infracfg = <&infracfg>;
288                        };
289                    };
290                };
291            };
292        };
293    };
294