1d392fe78SEnric Balletbo i Serra# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2d392fe78SEnric Balletbo i Serra%YAML 1.2 3d392fe78SEnric Balletbo i Serra--- 4d392fe78SEnric Balletbo i Serra$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml# 5d392fe78SEnric Balletbo i Serra$schema: http://devicetree.org/meta-schemas/core.yaml# 6d392fe78SEnric Balletbo i Serra 7d392fe78SEnric Balletbo i Serratitle: Mediatek Power Domains Controller 8d392fe78SEnric Balletbo i Serra 9d392fe78SEnric Balletbo i Serramaintainers: 10d392fe78SEnric Balletbo i Serra - Weiyi Lu <weiyi.lu@mediatek.com> 11d392fe78SEnric Balletbo i Serra - Matthias Brugger <mbrugger@suse.com> 12d392fe78SEnric Balletbo i Serra 13d392fe78SEnric Balletbo i Serradescription: | 14d392fe78SEnric Balletbo i Serra Mediatek processors include support for multiple power domains which can be 15d392fe78SEnric Balletbo i Serra powered up/down by software based on different application scenes to save power. 16d392fe78SEnric Balletbo i Serra 17d392fe78SEnric Balletbo i Serra IP cores belonging to a power domain should contain a 'power-domains' 18d392fe78SEnric Balletbo i Serra property that is a phandle for SCPSYS node representing the domain. 19d392fe78SEnric Balletbo i Serra 20d392fe78SEnric Balletbo i Serraproperties: 21d392fe78SEnric Balletbo i Serra $nodename: 22d392fe78SEnric Balletbo i Serra const: power-controller 23d392fe78SEnric Balletbo i Serra 24d392fe78SEnric Balletbo i Serra compatible: 25d392fe78SEnric Balletbo i Serra enum: 262b48db01SAngeloGioacchino Del Regno - mediatek,mt6795-power-controller 27c70d0f16SFabien Parent - mediatek,mt8167-power-controller 28d392fe78SEnric Balletbo i Serra - mediatek,mt8173-power-controller 2986a378bbSEnric Balletbo i Serra - mediatek,mt8183-power-controller 30c8a00689SChun-Jie Chen - mediatek,mt8186-power-controller 31343106d9SWeiyi Lu - mediatek,mt8192-power-controller 3273c022e1SChun-Jie Chen - mediatek,mt8195-power-controller 33d392fe78SEnric Balletbo i Serra 34d392fe78SEnric Balletbo i Serra '#power-domain-cells': 35d392fe78SEnric Balletbo i Serra const: 1 36d392fe78SEnric Balletbo i Serra 37d392fe78SEnric Balletbo i Serra '#address-cells': 38d392fe78SEnric Balletbo i Serra const: 1 39d392fe78SEnric Balletbo i Serra 40d392fe78SEnric Balletbo i Serra '#size-cells': 41d392fe78SEnric Balletbo i Serra const: 0 42d392fe78SEnric Balletbo i Serra 43d392fe78SEnric Balletbo i SerrapatternProperties: 44d392fe78SEnric Balletbo i Serra "^power-domain@[0-9a-f]+$": 45d392fe78SEnric Balletbo i Serra type: object 46d392fe78SEnric Balletbo i Serra description: | 47d392fe78SEnric Balletbo i Serra Represents the power domains within the power controller node as documented 48d392fe78SEnric Balletbo i Serra in Documentation/devicetree/bindings/power/power-domain.yaml. 49d392fe78SEnric Balletbo i Serra 50d392fe78SEnric Balletbo i Serra properties: 51d392fe78SEnric Balletbo i Serra 52d392fe78SEnric Balletbo i Serra '#power-domain-cells': 53d392fe78SEnric Balletbo i Serra description: 54d392fe78SEnric Balletbo i Serra Must be 0 for nodes representing a single PM domain and 1 for nodes 55d392fe78SEnric Balletbo i Serra providing multiple PM domains. 56d392fe78SEnric Balletbo i Serra 57d392fe78SEnric Balletbo i Serra '#address-cells': 58d392fe78SEnric Balletbo i Serra const: 1 59d392fe78SEnric Balletbo i Serra 60d392fe78SEnric Balletbo i Serra '#size-cells': 61d392fe78SEnric Balletbo i Serra const: 0 62d392fe78SEnric Balletbo i Serra 63d392fe78SEnric Balletbo i Serra reg: 64d392fe78SEnric Balletbo i Serra description: | 65d392fe78SEnric Balletbo i Serra Power domain index. Valid values are defined in: 662b48db01SAngeloGioacchino Del Regno "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain. 67c70d0f16SFabien Parent "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain. 68d392fe78SEnric Balletbo i Serra "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. 6986a378bbSEnric Balletbo i Serra "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. 70343106d9SWeiyi Lu "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain. 7173c022e1SChun-Jie Chen "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain. 72d392fe78SEnric Balletbo i Serra maxItems: 1 73d392fe78SEnric Balletbo i Serra 74d392fe78SEnric Balletbo i Serra clocks: 75d392fe78SEnric Balletbo i Serra description: | 76d392fe78SEnric Balletbo i Serra A number of phandles to clocks that need to be enabled during domain 77d392fe78SEnric Balletbo i Serra power-up sequencing. 78d392fe78SEnric Balletbo i Serra 79d392fe78SEnric Balletbo i Serra clock-names: 80d392fe78SEnric Balletbo i Serra description: | 81d392fe78SEnric Balletbo i Serra List of names of clocks, in order to match the power-up sequencing 82d392fe78SEnric Balletbo i Serra for each power domain we need to group the clocks by name. BASIC 83d392fe78SEnric Balletbo i Serra clocks need to be enabled before enabling the corresponding power 84d392fe78SEnric Balletbo i Serra domain, and should not have a '-' in their name (i.e mm, mfg, venc). 85d392fe78SEnric Balletbo i Serra SUSBYS clocks need to be enabled before releasing the bus protection, 86d392fe78SEnric Balletbo i Serra and should contain a '-' in their name (i.e mm-0, isp-0, cam-0). 87d392fe78SEnric Balletbo i Serra 88d392fe78SEnric Balletbo i Serra In order to follow properly the power-up sequencing, the clocks must 89d392fe78SEnric Balletbo i Serra be specified by order, adding first the BASIC clocks followed by the 90d392fe78SEnric Balletbo i Serra SUSBSYS clocks. 91d392fe78SEnric Balletbo i Serra 92ebfe73f7SHsin-Yi Wang domain-supply: 93ebfe73f7SHsin-Yi Wang description: domain regulator supply. 94d392fe78SEnric Balletbo i Serra 95d392fe78SEnric Balletbo i Serra mediatek,infracfg: 96d69c6dddSRob Herring $ref: /schemas/types.yaml#/definitions/phandle 97d392fe78SEnric Balletbo i Serra description: phandle to the device containing the INFRACFG register range. 98d392fe78SEnric Balletbo i Serra 99d392fe78SEnric Balletbo i Serra mediatek,smi: 100d69c6dddSRob Herring $ref: /schemas/types.yaml#/definitions/phandle 101d392fe78SEnric Balletbo i Serra description: phandle to the device containing the SMI register range. 102d392fe78SEnric Balletbo i Serra 103d392fe78SEnric Balletbo i Serra patternProperties: 104d392fe78SEnric Balletbo i Serra "^power-domain@[0-9a-f]+$": 105d392fe78SEnric Balletbo i Serra type: object 106d392fe78SEnric Balletbo i Serra description: | 107d392fe78SEnric Balletbo i Serra Represents a power domain child within a power domain parent node. 108d392fe78SEnric Balletbo i Serra 109d392fe78SEnric Balletbo i Serra properties: 110d392fe78SEnric Balletbo i Serra 111d392fe78SEnric Balletbo i Serra '#power-domain-cells': 112d392fe78SEnric Balletbo i Serra description: 113d392fe78SEnric Balletbo i Serra Must be 0 for nodes representing a single PM domain and 1 for nodes 114d392fe78SEnric Balletbo i Serra providing multiple PM domains. 115d392fe78SEnric Balletbo i Serra 116d392fe78SEnric Balletbo i Serra '#address-cells': 117d392fe78SEnric Balletbo i Serra const: 1 118d392fe78SEnric Balletbo i Serra 119d392fe78SEnric Balletbo i Serra '#size-cells': 120d392fe78SEnric Balletbo i Serra const: 0 121d392fe78SEnric Balletbo i Serra 122d392fe78SEnric Balletbo i Serra reg: 123d392fe78SEnric Balletbo i Serra maxItems: 1 124d392fe78SEnric Balletbo i Serra 125d392fe78SEnric Balletbo i Serra clocks: 126d392fe78SEnric Balletbo i Serra description: | 127d392fe78SEnric Balletbo i Serra A number of phandles to clocks that need to be enabled during domain 128d392fe78SEnric Balletbo i Serra power-up sequencing. 129d392fe78SEnric Balletbo i Serra 130d392fe78SEnric Balletbo i Serra clock-names: 131d392fe78SEnric Balletbo i Serra description: | 132d392fe78SEnric Balletbo i Serra List of names of clocks, in order to match the power-up sequencing 133d392fe78SEnric Balletbo i Serra for each power domain we need to group the clocks by name. BASIC 134d392fe78SEnric Balletbo i Serra clocks need to be enabled before enabling the corresponding power 135d392fe78SEnric Balletbo i Serra domain, and should not have a '-' in their name (i.e mm, mfg, venc). 136d392fe78SEnric Balletbo i Serra SUSBYS clocks need to be enabled before releasing the bus protection, 137d392fe78SEnric Balletbo i Serra and should contain a '-' in their name (i.e mm-0, isp-0, cam-0). 138d392fe78SEnric Balletbo i Serra 139d392fe78SEnric Balletbo i Serra In order to follow properly the power-up sequencing, the clocks must 140d392fe78SEnric Balletbo i Serra be specified by order, adding first the BASIC clocks followed by the 141d392fe78SEnric Balletbo i Serra SUSBSYS clocks. 142d392fe78SEnric Balletbo i Serra 143ebfe73f7SHsin-Yi Wang domain-supply: 144ebfe73f7SHsin-Yi Wang description: domain regulator supply. 145ebfe73f7SHsin-Yi Wang 146ebfe73f7SHsin-Yi Wang mediatek,infracfg: 147ebfe73f7SHsin-Yi Wang $ref: /schemas/types.yaml#/definitions/phandle 148ebfe73f7SHsin-Yi Wang description: phandle to the device containing the INFRACFG register range. 149ebfe73f7SHsin-Yi Wang 150ebfe73f7SHsin-Yi Wang mediatek,smi: 151ebfe73f7SHsin-Yi Wang $ref: /schemas/types.yaml#/definitions/phandle 152ebfe73f7SHsin-Yi Wang description: phandle to the device containing the SMI register range. 153ebfe73f7SHsin-Yi Wang 154ebfe73f7SHsin-Yi Wang patternProperties: 155ebfe73f7SHsin-Yi Wang "^power-domain@[0-9a-f]+$": 156ebfe73f7SHsin-Yi Wang type: object 157ebfe73f7SHsin-Yi Wang description: | 158ebfe73f7SHsin-Yi Wang Represents a power domain child within a power domain parent node. 159ebfe73f7SHsin-Yi Wang 160ebfe73f7SHsin-Yi Wang properties: 161ebfe73f7SHsin-Yi Wang 162ebfe73f7SHsin-Yi Wang '#power-domain-cells': 163ebfe73f7SHsin-Yi Wang description: 164ebfe73f7SHsin-Yi Wang Must be 0 for nodes representing a single PM domain and 1 for nodes 165ebfe73f7SHsin-Yi Wang providing multiple PM domains. 166ebfe73f7SHsin-Yi Wang 167ebfe73f7SHsin-Yi Wang '#address-cells': 168ebfe73f7SHsin-Yi Wang const: 1 169ebfe73f7SHsin-Yi Wang 170ebfe73f7SHsin-Yi Wang '#size-cells': 171ebfe73f7SHsin-Yi Wang const: 0 172ebfe73f7SHsin-Yi Wang 173ebfe73f7SHsin-Yi Wang reg: 174ebfe73f7SHsin-Yi Wang maxItems: 1 175ebfe73f7SHsin-Yi Wang 176ebfe73f7SHsin-Yi Wang clocks: 177ebfe73f7SHsin-Yi Wang description: | 178ebfe73f7SHsin-Yi Wang A number of phandles to clocks that need to be enabled during domain 179ebfe73f7SHsin-Yi Wang power-up sequencing. 180ebfe73f7SHsin-Yi Wang 181ebfe73f7SHsin-Yi Wang clock-names: 182ebfe73f7SHsin-Yi Wang description: | 183ebfe73f7SHsin-Yi Wang List of names of clocks, in order to match the power-up sequencing 184ebfe73f7SHsin-Yi Wang for each power domain we need to group the clocks by name. BASIC 185ebfe73f7SHsin-Yi Wang clocks need to be enabled before enabling the corresponding power 186ebfe73f7SHsin-Yi Wang domain, and should not have a '-' in their name (i.e mm, mfg, venc). 187ebfe73f7SHsin-Yi Wang SUSBYS clocks need to be enabled before releasing the bus protection, 188ebfe73f7SHsin-Yi Wang and should contain a '-' in their name (i.e mm-0, isp-0, cam-0). 189ebfe73f7SHsin-Yi Wang 190ebfe73f7SHsin-Yi Wang In order to follow properly the power-up sequencing, the clocks must 191ebfe73f7SHsin-Yi Wang be specified by order, adding first the BASIC clocks followed by the 192ebfe73f7SHsin-Yi Wang SUSBSYS clocks. 193ebfe73f7SHsin-Yi Wang 194ebfe73f7SHsin-Yi Wang domain-supply: 195ebfe73f7SHsin-Yi Wang description: domain regulator supply. 196ebfe73f7SHsin-Yi Wang 197d392fe78SEnric Balletbo i Serra mediatek,infracfg: 198d69c6dddSRob Herring $ref: /schemas/types.yaml#/definitions/phandle 199d392fe78SEnric Balletbo i Serra description: phandle to the device containing the INFRACFG register range. 200d392fe78SEnric Balletbo i Serra 201d392fe78SEnric Balletbo i Serra mediatek,smi: 202d69c6dddSRob Herring $ref: /schemas/types.yaml#/definitions/phandle 203d392fe78SEnric Balletbo i Serra description: phandle to the device containing the SMI register range. 204d392fe78SEnric Balletbo i Serra 205d392fe78SEnric Balletbo i Serra required: 206d392fe78SEnric Balletbo i Serra - reg 207d392fe78SEnric Balletbo i Serra 208d392fe78SEnric Balletbo i Serra additionalProperties: false 209d392fe78SEnric Balletbo i Serra 210d392fe78SEnric Balletbo i Serra required: 211d392fe78SEnric Balletbo i Serra - reg 212d392fe78SEnric Balletbo i Serra 213d392fe78SEnric Balletbo i Serra additionalProperties: false 214d392fe78SEnric Balletbo i Serra 215d392fe78SEnric Balletbo i Serra required: 216d392fe78SEnric Balletbo i Serra - reg 217d392fe78SEnric Balletbo i Serra 218d392fe78SEnric Balletbo i Serra additionalProperties: false 219d392fe78SEnric Balletbo i Serra 220d392fe78SEnric Balletbo i Serrarequired: 221d392fe78SEnric Balletbo i Serra - compatible 222d392fe78SEnric Balletbo i Serra 223d392fe78SEnric Balletbo i SerraadditionalProperties: false 224d392fe78SEnric Balletbo i Serra 225d392fe78SEnric Balletbo i Serraexamples: 226d392fe78SEnric Balletbo i Serra - | 227d392fe78SEnric Balletbo i Serra #include <dt-bindings/clock/mt8173-clk.h> 228d392fe78SEnric Balletbo i Serra #include <dt-bindings/power/mt8173-power.h> 229d392fe78SEnric Balletbo i Serra 230d392fe78SEnric Balletbo i Serra soc { 231d392fe78SEnric Balletbo i Serra #address-cells = <2>; 232d392fe78SEnric Balletbo i Serra #size-cells = <2>; 233d392fe78SEnric Balletbo i Serra 234d392fe78SEnric Balletbo i Serra scpsys: syscon@10006000 { 235*26331d26STinghan Shen compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd"; 236d392fe78SEnric Balletbo i Serra reg = <0 0x10006000 0 0x1000>; 237d392fe78SEnric Balletbo i Serra 238d392fe78SEnric Balletbo i Serra spm: power-controller { 239d392fe78SEnric Balletbo i Serra compatible = "mediatek,mt8173-power-controller"; 240d392fe78SEnric Balletbo i Serra #address-cells = <1>; 241d392fe78SEnric Balletbo i Serra #size-cells = <0>; 242d392fe78SEnric Balletbo i Serra #power-domain-cells = <1>; 243d392fe78SEnric Balletbo i Serra 244d392fe78SEnric Balletbo i Serra /* power domains of the SoC */ 245d392fe78SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_VDEC { 246d392fe78SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_VDEC>; 247d392fe78SEnric Balletbo i Serra clocks = <&topckgen CLK_TOP_MM_SEL>; 248d392fe78SEnric Balletbo i Serra clock-names = "mm"; 249d392fe78SEnric Balletbo i Serra #power-domain-cells = <0>; 250d392fe78SEnric Balletbo i Serra }; 251d392fe78SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_VENC { 252d392fe78SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_VENC>; 253d392fe78SEnric Balletbo i Serra clocks = <&topckgen CLK_TOP_MM_SEL>, 254d392fe78SEnric Balletbo i Serra <&topckgen CLK_TOP_VENC_SEL>; 255d392fe78SEnric Balletbo i Serra clock-names = "mm", "venc"; 256d392fe78SEnric Balletbo i Serra #power-domain-cells = <0>; 257d392fe78SEnric Balletbo i Serra }; 258d392fe78SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_ISP { 259d392fe78SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_ISP>; 260d392fe78SEnric Balletbo i Serra clocks = <&topckgen CLK_TOP_MM_SEL>; 261d392fe78SEnric Balletbo i Serra clock-names = "mm"; 262d392fe78SEnric Balletbo i Serra #power-domain-cells = <0>; 263d392fe78SEnric Balletbo i Serra }; 264d392fe78SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_MM { 265d392fe78SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_MM>; 266d392fe78SEnric Balletbo i Serra clocks = <&topckgen CLK_TOP_MM_SEL>; 267d392fe78SEnric Balletbo i Serra clock-names = "mm"; 268d392fe78SEnric Balletbo i Serra #power-domain-cells = <0>; 269d392fe78SEnric Balletbo i Serra mediatek,infracfg = <&infracfg>; 270d392fe78SEnric Balletbo i Serra }; 271d392fe78SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_VENC_LT { 272d392fe78SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_VENC_LT>; 273d392fe78SEnric Balletbo i Serra clocks = <&topckgen CLK_TOP_MM_SEL>, 274d392fe78SEnric Balletbo i Serra <&topckgen CLK_TOP_VENC_LT_SEL>; 275d392fe78SEnric Balletbo i Serra clock-names = "mm", "venclt"; 276d392fe78SEnric Balletbo i Serra #power-domain-cells = <0>; 277d392fe78SEnric Balletbo i Serra }; 278d392fe78SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_AUDIO { 279d392fe78SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_AUDIO>; 280d392fe78SEnric Balletbo i Serra #power-domain-cells = <0>; 281d392fe78SEnric Balletbo i Serra }; 282d392fe78SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_USB { 283d392fe78SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_USB>; 284d392fe78SEnric Balletbo i Serra #power-domain-cells = <0>; 285d392fe78SEnric Balletbo i Serra }; 286d392fe78SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC { 287d392fe78SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>; 288d392fe78SEnric Balletbo i Serra clocks = <&clk26m>; 289d392fe78SEnric Balletbo i Serra clock-names = "mfg"; 290d392fe78SEnric Balletbo i Serra #address-cells = <1>; 291d392fe78SEnric Balletbo i Serra #size-cells = <0>; 292d392fe78SEnric Balletbo i Serra #power-domain-cells = <1>; 293d392fe78SEnric Balletbo i Serra 294d392fe78SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_MFG_2D { 295d392fe78SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_MFG_2D>; 296d392fe78SEnric Balletbo i Serra #address-cells = <1>; 297d392fe78SEnric Balletbo i Serra #size-cells = <0>; 298d392fe78SEnric Balletbo i Serra #power-domain-cells = <1>; 299d392fe78SEnric Balletbo i Serra 300d392fe78SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_MFG { 301d392fe78SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_MFG>; 302d392fe78SEnric Balletbo i Serra #power-domain-cells = <0>; 303d392fe78SEnric Balletbo i Serra mediatek,infracfg = <&infracfg>; 304d392fe78SEnric Balletbo i Serra }; 305d392fe78SEnric Balletbo i Serra }; 306d392fe78SEnric Balletbo i Serra }; 307d392fe78SEnric Balletbo i Serra }; 308d392fe78SEnric Balletbo i Serra }; 309d392fe78SEnric Balletbo i Serra }; 310