1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Xilinx ZynqMP Pinctrl
8
9maintainers:
10  - Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
11  - Rajan Vaja <rajan.vaja@xilinx.com>
12
13description: |
14  Please refer to pinctrl-bindings.txt in this directory for details of the
15  common pinctrl bindings used by client devices, including the meaning of the
16  phrase "pin configuration node".
17
18  ZynqMP's pin configuration nodes act as a container for an arbitrary number of
19  subnodes. Each of these subnodes represents some desired configuration for a
20  pin, a group, or a list of pins or groups. This configuration can include the
21  mux function to select on those pin(s)/group(s), and various pin configuration
22  parameters, such as pull-up, slew rate, etc.
23
24  Each configuration node can consist of multiple nodes describing the pinmux and
25  pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
26
27  The name of each subnode is not important; all subnodes should be enumerated
28  and processed purely based on their content.
29
30properties:
31  compatible:
32    const: xlnx,zynqmp-pinctrl
33
34patternProperties:
35  '^(.*-)?(default|gpio)$':
36    type: object
37    patternProperties:
38      '^mux':
39        type: object
40        description:
41          Pinctrl node's client devices use subnodes for pin muxes,
42          which in turn use below standard properties.
43        $ref: pinmux-node.yaml#
44
45        properties:
46          groups:
47            description:
48              List of groups to select (either this or "pins" must be
49              specified), available groups for this subnode.
50            items:
51              enum: [ethernet0_0_grp, ethernet1_0_grp, ethernet2_0_grp,
52                     ethernet3_0_grp, gemtsu0_0_grp, gemtsu0_1_grp,
53                     gemtsu0_2_grp, mdio0_0_grp, mdio1_0_grp,
54                     mdio1_1_grp, mdio2_0_grp, mdio3_0_grp,
55                     qspi0_0_grp, qspi_ss_0_grp, qspi_fbclk_0_grp,
56                     spi0_0_grp, spi0_ss_0_grp, spi0_ss_1_grp,
57                     spi0_ss_2_grp, spi0_1_grp, spi0_ss_3_grp,
58                     spi0_ss_4_grp, spi0_ss_5_grp, spi0_2_grp,
59                     spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp,
60                     spi0_3_grp, spi0_ss_9_grp, spi0_ss_10_grp,
61                     spi0_ss_11_grp, spi0_4_grp, spi0_ss_12_grp,
62                     spi0_ss_13_grp, spi0_ss_14_grp, spi0_5_grp,
63                     spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp,
64                     spi1_0_grp, spi1_ss_0_grp, spi1_ss_1_grp,
65                     spi1_ss_2_grp, spi1_1_grp, spi1_ss_3_grp,
66                     spi1_ss_4_grp, spi1_ss_5_grp, spi1_2_grp,
67                     spi1_ss_6_grp, spi1_ss_7_grp, spi1_ss_8_grp,
68                     spi1_3_grp, spi1_ss_9_grp, spi1_ss_10_grp,
69                     spi1_ss_11_grp, spi1_4_grp, spi1_ss_12_grp,
70                     spi1_ss_13_grp, spi1_ss_14_grp, spi1_5_grp,
71                     spi1_ss_15_grp, spi1_ss_16_grp, spi1_ss_17_grp,
72                     sdio0_0_grp, sdio0_1_grp, sdio0_2_grp,
73                     sdio0_3_grp, sdio0_4_grp, sdio0_5_grp,
74                     sdio0_6_grp, sdio0_7_grp, sdio0_8_grp,
75                     sdio0_9_grp, sdio0_10_grp, sdio0_11_grp,
76                     sdio0_12_grp, sdio0_13_grp, sdio0_14_grp,
77                     sdio0_15_grp, sdio0_16_grp, sdio0_17_grp,
78                     sdio0_18_grp, sdio0_19_grp, sdio0_20_grp,
79                     sdio0_21_grp, sdio0_22_grp, sdio0_23_grp,
80                     sdio0_24_grp, sdio0_25_grp, sdio0_26_grp,
81                     sdio0_27_grp, sdio0_28_grp, sdio0_29_grp,
82                     sdio0_30_grp, sdio0_31_grp, sdio0_32_grp,
83                     sdio0_pc_0_grp, sdio0_cd_0_grp, sdio0_wp_0_grp,
84                     sdio0_pc_1_grp, sdio0_cd_1_grp, sdio0_wp_1_grp,
85                     sdio0_pc_2_grp, sdio0_cd_2_grp, sdio0_wp_2_grp,
86                     sdio1_0_grp, sdio1_1_grp, sdio1_2_grp,
87                     sdio1_3_grp, sdio1_4_grp, sdio1_5_grp,
88                     sdio1_6_grp, sdio1_7_grp, sdio1_8_grp,
89                     sdio1_9_grp, sdio1_10_grp, sdio1_11_grp,
90                     sdio1_12_grp, sdio1_13_grp, sdio1_14_grp,
91                     sdio1_15_grp, sdio1_pc_0_grp, sdio1_cd_0_grp,
92                     sdio1_wp_0_grp, sdio1_pc_1_grp, sdio1_cd_1_grp,
93                     sdio1_wp_1_grp, nand0_0_grp, nand0_ce_0_grp,
94                     nand0_rb_0_grp, nand0_dqs_0_grp, nand0_ce_1_grp,
95                     nand0_rb_1_grp, nand0_dqs_1_grp, can0_0_grp,
96                     can0_1_grp, can0_2_grp, can0_3_grp,
97                     can0_4_grp, can0_5_grp, can0_6_grp,
98                     can0_7_grp, can0_8_grp, can0_9_grp,
99                     can0_10_grp, can0_11_grp, can0_12_grp,
100                     can0_13_grp, can0_14_grp, can0_15_grp,
101                     can0_16_grp, can0_17_grp, can0_18_grp,
102                     can1_0_grp, can1_1_grp, can1_2_grp,
103                     can1_3_grp, can1_4_grp, can1_5_grp,
104                     can1_6_grp, can1_7_grp, can1_8_grp,
105                     can1_9_grp, can1_10_grp, can1_11_grp,
106                     can1_12_grp, can1_13_grp, can1_14_grp,
107                     can1_15_grp, can1_16_grp, can1_17_grp,
108                     can1_18_grp, can1_19_grp, uart0_0_grp,
109                     uart0_1_grp, uart0_2_grp, uart0_3_grp,
110                     uart0_4_grp, uart0_5_grp, uart0_6_grp,
111                     uart0_7_grp, uart0_8_grp, uart0_9_grp,
112                     uart0_10_grp, uart0_11_grp, uart0_12_grp,
113                     uart0_13_grp, uart0_14_grp, uart0_15_grp,
114                     uart0_16_grp, uart0_17_grp, uart0_18_grp,
115                     uart1_0_grp, uart1_1_grp, uart1_2_grp,
116                     uart1_3_grp, uart1_4_grp, uart1_5_grp,
117                     uart1_6_grp, uart1_7_grp, uart1_8_grp,
118                     uart1_9_grp, uart1_10_grp, uart1_11_grp,
119                     uart1_12_grp, uart1_13_grp, uart1_14_grp,
120                     uart1_15_grp, uart1_16_grp, uart1_17_grp,
121                     uart1_18_grp, i2c0_0_grp, i2c0_1_grp,
122                     i2c0_2_grp, i2c0_3_grp, i2c0_4_grp,
123                     i2c0_5_grp, i2c0_6_grp, i2c0_7_grp,
124                     i2c0_8_grp, i2c0_9_grp, i2c0_10_grp,
125                     i2c0_11_grp, i2c0_12_grp, i2c0_13_grp,
126                     i2c0_14_grp, i2c0_15_grp, i2c0_16_grp,
127                     i2c0_17_grp, i2c0_18_grp, i2c1_0_grp,
128                     i2c1_1_grp, i2c1_2_grp, i2c1_3_grp,
129                     i2c1_4_grp, i2c1_5_grp, i2c1_6_grp,
130                     i2c1_7_grp, i2c1_8_grp, i2c1_9_grp,
131                     i2c1_10_grp, i2c1_11_grp, i2c1_12_grp,
132                     i2c1_13_grp, i2c1_14_grp, i2c1_15_grp,
133                     i2c1_16_grp, i2c1_17_grp, i2c1_18_grp,
134                     i2c1_19_grp, ttc0_clk_0_grp, ttc0_wav_0_grp,
135                     ttc0_clk_1_grp, ttc0_wav_1_grp, ttc0_clk_2_grp,
136                     ttc0_wav_2_grp, ttc0_clk_3_grp, ttc0_wav_3_grp,
137                     ttc0_clk_4_grp, ttc0_wav_4_grp, ttc0_clk_5_grp,
138                     ttc0_wav_5_grp, ttc0_clk_6_grp, ttc0_wav_6_grp,
139                     ttc0_clk_7_grp, ttc0_wav_7_grp, ttc0_clk_8_grp,
140                     ttc0_wav_8_grp, ttc1_clk_0_grp, ttc1_wav_0_grp,
141                     ttc1_clk_1_grp, ttc1_wav_1_grp, ttc1_clk_2_grp,
142                     ttc1_wav_2_grp, ttc1_clk_3_grp, ttc1_wav_3_grp,
143                     ttc1_clk_4_grp, ttc1_wav_4_grp, ttc1_clk_5_grp,
144                     ttc1_wav_5_grp, ttc1_clk_6_grp, ttc1_wav_6_grp,
145                     ttc1_clk_7_grp, ttc1_wav_7_grp, ttc1_clk_8_grp,
146                     ttc1_wav_8_grp, ttc2_clk_0_grp, ttc2_wav_0_grp,
147                     ttc2_clk_1_grp, ttc2_wav_1_grp, ttc2_clk_2_grp,
148                     ttc2_wav_2_grp, ttc2_clk_3_grp, ttc2_wav_3_grp,
149                     ttc2_clk_4_grp, ttc2_wav_4_grp, ttc2_clk_5_grp,
150                     ttc2_wav_5_grp, ttc2_clk_6_grp, ttc2_wav_6_grp,
151                     ttc2_clk_7_grp, ttc2_wav_7_grp, ttc2_clk_8_grp,
152                     ttc2_wav_8_grp, ttc3_clk_0_grp, ttc3_wav_0_grp,
153                     ttc3_clk_1_grp, ttc3_wav_1_grp, ttc3_clk_2_grp,
154                     ttc3_wav_2_grp, ttc3_clk_3_grp, ttc3_wav_3_grp,
155                     ttc3_clk_4_grp, ttc3_wav_4_grp, ttc3_clk_5_grp,
156                     ttc3_wav_5_grp, ttc3_clk_6_grp, ttc3_wav_6_grp,
157                     ttc3_clk_7_grp, ttc3_wav_7_grp, ttc3_clk_8_grp,
158                     ttc3_wav_8_grp, swdt0_clk_0_grp, swdt0_rst_0_grp,
159                     swdt0_clk_1_grp, swdt0_rst_1_grp, swdt0_clk_2_grp,
160                     swdt0_rst_2_grp, swdt0_clk_3_grp, swdt0_rst_3_grp,
161                     swdt0_clk_4_grp, swdt0_rst_4_grp, swdt0_clk_5_grp,
162                     swdt0_rst_5_grp, swdt0_clk_6_grp, swdt0_rst_6_grp,
163                     swdt0_clk_7_grp, swdt0_rst_7_grp, swdt0_clk_8_grp,
164                     swdt0_rst_8_grp, swdt0_clk_9_grp, swdt0_rst_9_grp,
165                     swdt0_clk_10_grp, swdt0_rst_10_grp, swdt0_clk_11_grp,
166                     swdt0_rst_11_grp, swdt0_clk_12_grp, swdt0_rst_12_grp,
167                     swdt1_clk_0_grp, swdt1_rst_0_grp, swdt1_clk_1_grp,
168                     swdt1_rst_1_grp, swdt1_clk_2_grp, swdt1_rst_2_grp,
169                     swdt1_clk_3_grp, swdt1_rst_3_grp, swdt1_clk_4_grp,
170                     swdt1_rst_4_grp, swdt1_clk_5_grp, swdt1_rst_5_grp,
171                     swdt1_clk_6_grp, swdt1_rst_6_grp, swdt1_clk_7_grp,
172                     swdt1_rst_7_grp, swdt1_clk_8_grp, swdt1_rst_8_grp,
173                     swdt1_clk_9_grp, swdt1_rst_9_grp, swdt1_clk_10_grp,
174                     swdt1_rst_10_grp, swdt1_clk_11_grp, swdt1_rst_11_grp,
175                     swdt1_clk_12_grp, swdt1_rst_12_grp, gpio0_0_grp,
176                     gpio0_1_grp, gpio0_2_grp, gpio0_3_grp,
177                     gpio0_4_grp, gpio0_5_grp, gpio0_6_grp,
178                     gpio0_7_grp, gpio0_8_grp, gpio0_9_grp,
179                     gpio0_10_grp, gpio0_11_grp, gpio0_12_grp,
180                     gpio0_13_grp, gpio0_14_grp, gpio0_15_grp,
181                     gpio0_16_grp, gpio0_17_grp, gpio0_18_grp,
182                     gpio0_19_grp, gpio0_20_grp, gpio0_21_grp,
183                     gpio0_22_grp, gpio0_23_grp, gpio0_24_grp,
184                     gpio0_25_grp, gpio0_26_grp, gpio0_27_grp,
185                     gpio0_28_grp, gpio0_29_grp, gpio0_30_grp,
186                     gpio0_31_grp, gpio0_32_grp, gpio0_33_grp,
187                     gpio0_34_grp, gpio0_35_grp, gpio0_36_grp,
188                     gpio0_37_grp, gpio0_38_grp, gpio0_39_grp,
189                     gpio0_40_grp, gpio0_41_grp, gpio0_42_grp,
190                     gpio0_43_grp, gpio0_44_grp, gpio0_45_grp,
191                     gpio0_46_grp, gpio0_47_grp, gpio0_48_grp,
192                     gpio0_49_grp, gpio0_50_grp, gpio0_51_grp,
193                     gpio0_52_grp, gpio0_53_grp, gpio0_54_grp,
194                     gpio0_55_grp, gpio0_56_grp, gpio0_57_grp,
195                     gpio0_58_grp, gpio0_59_grp, gpio0_60_grp,
196                     gpio0_61_grp, gpio0_62_grp, gpio0_63_grp,
197                     gpio0_64_grp, gpio0_65_grp, gpio0_66_grp,
198                     gpio0_67_grp, gpio0_68_grp, gpio0_69_grp,
199                     gpio0_70_grp, gpio0_71_grp, gpio0_72_grp,
200                     gpio0_73_grp, gpio0_74_grp, gpio0_75_grp,
201                     gpio0_76_grp, gpio0_77_grp, usb0_0_grp,
202                     usb1_0_grp, pmu0_0_grp, pmu0_1_grp,
203                     pmu0_2_grp, pmu0_3_grp, pmu0_4_grp,
204                     pmu0_5_grp, pmu0_6_grp, pmu0_7_grp,
205                     pmu0_8_grp, pmu0_9_grp, pmu0_10_grp,
206                     pmu0_11_grp, pcie0_0_grp, pcie0_1_grp,
207                     pcie0_2_grp, pcie0_3_grp, pcie0_4_grp,
208                     pcie0_5_grp, pcie0_6_grp, pcie0_7_grp,
209                     csu0_0_grp, csu0_1_grp, csu0_2_grp,
210                     csu0_3_grp, csu0_4_grp, csu0_5_grp,
211                     csu0_6_grp, csu0_7_grp, csu0_8_grp,
212                     csu0_9_grp, csu0_10_grp, csu0_11_grp,
213                     dpaux0_0_grp, dpaux0_1_grp, dpaux0_2_grp,
214                     dpaux0_3_grp, pjtag0_0_grp, pjtag0_1_grp,
215                     pjtag0_2_grp, pjtag0_3_grp, pjtag0_4_grp,
216                     pjtag0_5_grp, trace0_0_grp, trace0_clk_0_grp,
217                     trace0_1_grp, trace0_clk_1_grp, trace0_2_grp,
218                     trace0_clk_2_grp, testscan0_0_grp]
219            maxItems: 78
220
221          function:
222            description:
223              Specify the alternative function to be configured for the
224              given pin groups.
225            enum: [ethernet0, ethernet1, ethernet2, ethernet3, gemtsu0, usb0, usb1, mdio0,
226                   mdio1, mdio2, mdio3, qspi0, qspi_fbclk, qspi_ss, spi0, spi1, spi0_ss,
227                   spi1_ss, sdio0, sdio0_pc, sdio0_wp, sdio0_cd, sdio1, sdio1_pc, sdio1_wp,
228                   sdio1_cd, nand0, nand0_ce, nand0_rb, nand0_dqs, can0, can1, uart0, uart1,
229                   i2c0, i2c1, ttc0_clk, ttc0_wav, ttc1_clk, ttc1_wav, ttc2_clk, ttc2_wav,
230                   ttc3_clk, ttc3_wav, swdt0_clk, swdt0_rst, swdt1_clk, swdt1_rst, gpio0, pmu0,
231                   pcie0, csu0, dpaux0, pjtag0, trace0, trace0_clk, testscan0]
232
233        required:
234          - groups
235          - function
236
237        additionalProperties: false
238
239      '^conf':
240        type: object
241        description:
242          Pinctrl node's client devices use subnodes for pin configurations,
243          which in turn use the standard properties below.
244        $ref: pincfg-node.yaml#
245
246        properties:
247          groups:
248            description:
249              List of pin groups as mentioned above.
250
251          pins:
252            description:
253              List of pin names to select in this subnode.
254            items:
255              pattern: '^MIO([0-9]|[1-6][0-9]|7[0-7])$'
256            maxItems: 78
257
258          bias-pull-up: true
259
260          bias-pull-down: true
261
262          bias-disable: true
263
264          input-schmitt-enable: true
265
266          input-schmitt-disable: true
267
268          bias-high-impedance: true
269
270          low-power-enable: true
271
272          low-power-disable: true
273
274          slew-rate:
275            enum: [0, 1]
276
277          drive-strength:
278            description:
279              Selects the drive strength for MIO pins, in mA.
280            enum: [2, 4, 8, 12]
281
282          power-source:
283            enum: [0, 1]
284
285        oneOf:
286          - required: [ groups ]
287          - required: [ pins ]
288
289        additionalProperties: false
290
291    additionalProperties: false
292
293required:
294  - compatible
295
296additionalProperties: false
297
298examples:
299  - |
300    #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
301    zynqmp_firmware: zynqmp-firmware {
302        pinctrl0: pinctrl {
303          compatible = "xlnx,zynqmp-pinctrl";
304
305          pinctrl_uart1_default: uart1-default {
306             mux {
307                 groups = "uart0_4_grp", "uart0_5_grp";
308                 function = "uart0";
309             };
310
311             conf {
312                groups = "uart0_4_grp";
313                slew-rate = <SLEW_RATE_SLOW>;
314                power-source = <IO_STANDARD_LVCMOS18>;
315             };
316
317             conf-rx {
318                pins = "MIO18";
319                bias-pull-up;
320             };
321
322             conf-tx {
323                pins = "MIO19";
324                bias-disable;
325                input-schmitt-disable;
326             };
327          };
328        };
329    };
330
331    uart1 {
332         pinctrl-names = "default";
333         pinctrl-0 = <&pinctrl_uart1_default>;
334    };
335
336...
337