1*716129d3SJianlong Huang# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2*716129d3SJianlong Huang%YAML 1.2 3*716129d3SJianlong Huang--- 4*716129d3SJianlong Huang$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml# 5*716129d3SJianlong Huang$schema: http://devicetree.org/meta-schemas/core.yaml# 6*716129d3SJianlong Huang 7*716129d3SJianlong Huangtitle: StarFive JH7110 AON Pin Controller 8*716129d3SJianlong Huang 9*716129d3SJianlong Huangdescription: | 10*716129d3SJianlong Huang Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd. 11*716129d3SJianlong Huang 12*716129d3SJianlong Huang Out of the SoC's many pins only the ones named PAD_RGPIO0 to PAD_RGPIO3 13*716129d3SJianlong Huang can be multiplexed and have configurable bias, drive strength, 14*716129d3SJianlong Huang schmitt trigger etc. 15*716129d3SJianlong Huang Some peripherals such as PWM have their I/O go through the 4 "GPIOs". 16*716129d3SJianlong Huang 17*716129d3SJianlong Huangmaintainers: 18*716129d3SJianlong Huang - Jianlong Huang <jianlong.huang@starfivetech.com> 19*716129d3SJianlong Huang 20*716129d3SJianlong Huangproperties: 21*716129d3SJianlong Huang compatible: 22*716129d3SJianlong Huang const: starfive,jh7110-aon-pinctrl 23*716129d3SJianlong Huang 24*716129d3SJianlong Huang reg: 25*716129d3SJianlong Huang maxItems: 1 26*716129d3SJianlong Huang 27*716129d3SJianlong Huang resets: 28*716129d3SJianlong Huang maxItems: 1 29*716129d3SJianlong Huang 30*716129d3SJianlong Huang interrupts: 31*716129d3SJianlong Huang maxItems: 1 32*716129d3SJianlong Huang 33*716129d3SJianlong Huang interrupt-controller: true 34*716129d3SJianlong Huang 35*716129d3SJianlong Huang '#interrupt-cells': 36*716129d3SJianlong Huang const: 2 37*716129d3SJianlong Huang 38*716129d3SJianlong Huang gpio-controller: true 39*716129d3SJianlong Huang 40*716129d3SJianlong Huang '#gpio-cells': 41*716129d3SJianlong Huang const: 2 42*716129d3SJianlong Huang 43*716129d3SJianlong HuangpatternProperties: 44*716129d3SJianlong Huang '-[0-9]+$': 45*716129d3SJianlong Huang type: object 46*716129d3SJianlong Huang additionalProperties: false 47*716129d3SJianlong Huang patternProperties: 48*716129d3SJianlong Huang '-pins$': 49*716129d3SJianlong Huang type: object 50*716129d3SJianlong Huang description: | 51*716129d3SJianlong Huang A pinctrl node should contain at least one subnode representing the 52*716129d3SJianlong Huang pinctrl groups available on the machine. Each subnode will list the 53*716129d3SJianlong Huang pins it needs, and how they should be configured, with regard to 54*716129d3SJianlong Huang muxer configuration, bias, input enable/disable, input schmitt 55*716129d3SJianlong Huang trigger enable/disable, slew-rate and drive strength. 56*716129d3SJianlong Huang allOf: 57*716129d3SJianlong Huang - $ref: /schemas/pinctrl/pincfg-node.yaml 58*716129d3SJianlong Huang - $ref: /schemas/pinctrl/pinmux-node.yaml 59*716129d3SJianlong Huang additionalProperties: false 60*716129d3SJianlong Huang 61*716129d3SJianlong Huang properties: 62*716129d3SJianlong Huang pinmux: 63*716129d3SJianlong Huang description: | 64*716129d3SJianlong Huang The list of GPIOs and their mux settings that properties in the 65*716129d3SJianlong Huang node apply to. This should be set using the GPIOMUX macro. 66*716129d3SJianlong Huang 67*716129d3SJianlong Huang bias-disable: true 68*716129d3SJianlong Huang 69*716129d3SJianlong Huang bias-pull-up: 70*716129d3SJianlong Huang type: boolean 71*716129d3SJianlong Huang 72*716129d3SJianlong Huang bias-pull-down: 73*716129d3SJianlong Huang type: boolean 74*716129d3SJianlong Huang 75*716129d3SJianlong Huang drive-strength: 76*716129d3SJianlong Huang enum: [ 2, 4, 8, 12 ] 77*716129d3SJianlong Huang 78*716129d3SJianlong Huang input-enable: true 79*716129d3SJianlong Huang 80*716129d3SJianlong Huang input-disable: true 81*716129d3SJianlong Huang 82*716129d3SJianlong Huang input-schmitt-enable: true 83*716129d3SJianlong Huang 84*716129d3SJianlong Huang input-schmitt-disable: true 85*716129d3SJianlong Huang 86*716129d3SJianlong Huang slew-rate: 87*716129d3SJianlong Huang maximum: 1 88*716129d3SJianlong Huang 89*716129d3SJianlong Huangrequired: 90*716129d3SJianlong Huang - compatible 91*716129d3SJianlong Huang - reg 92*716129d3SJianlong Huang - interrupts 93*716129d3SJianlong Huang - interrupt-controller 94*716129d3SJianlong Huang - '#interrupt-cells' 95*716129d3SJianlong Huang - gpio-controller 96*716129d3SJianlong Huang - '#gpio-cells' 97*716129d3SJianlong Huang 98*716129d3SJianlong HuangadditionalProperties: false 99*716129d3SJianlong Huang 100*716129d3SJianlong Huangexamples: 101*716129d3SJianlong Huang - | 102*716129d3SJianlong Huang pinctrl@17020000 { 103*716129d3SJianlong Huang compatible = "starfive,jh7110-aon-pinctrl"; 104*716129d3SJianlong Huang reg = <0x17020000 0x10000>; 105*716129d3SJianlong Huang resets = <&aoncrg 2>; 106*716129d3SJianlong Huang interrupts = <85>; 107*716129d3SJianlong Huang interrupt-controller; 108*716129d3SJianlong Huang #interrupt-cells = <2>; 109*716129d3SJianlong Huang gpio-controller; 110*716129d3SJianlong Huang #gpio-cells = <2>; 111*716129d3SJianlong Huang 112*716129d3SJianlong Huang pwm-0 { 113*716129d3SJianlong Huang pwm-pins { 114*716129d3SJianlong Huang pinmux = <0xff030802>; 115*716129d3SJianlong Huang bias-disable; 116*716129d3SJianlong Huang drive-strength = <12>; 117*716129d3SJianlong Huang input-disable; 118*716129d3SJianlong Huang input-schmitt-disable; 119*716129d3SJianlong Huang slew-rate = <0>; 120*716129d3SJianlong Huang }; 121*716129d3SJianlong Huang }; 122*716129d3SJianlong Huang }; 123*716129d3SJianlong Huang 124*716129d3SJianlong Huang... 125