1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright (C) STMicroelectronics 2019.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: STM32 GPIO and Pin Mux/Config controller
9
10maintainers:
11  - Alexandre TORGUE <alexandre.torgue@st.com>
12
13description: |
14  STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
15  controller. It controls the input/output settings on the available pins and
16  also provides ability to multiplex and configure the output of various
17  on-chip controllers onto these pads.
18
19properties:
20  compatible:
21    enum:
22      - st,stm32f429-pinctrl
23      - st,stm32f469-pinctrl
24      - st,stm32f746-pinctrl
25      - st,stm32f769-pinctrl
26      - st,stm32h743-pinctrl
27      - st,stm32mp157-pinctrl
28      - st,stm32mp157-z-pinctrl
29
30  '#address-cells':
31    const: 1
32  '#size-cells':
33    const: 1
34
35  ranges: true
36  pins-are-numbered: true
37  hwlocks: true
38
39  st,syscfg:
40    allOf:
41      - $ref: "/schemas/types.yaml#/definitions/phandle-array"
42    description: Should be phandle/offset/mask
43    items:
44      - description: Phandle to the syscon node which includes IRQ mux selection.
45      - description: The offset of the IRQ mux selection register.
46      - description: The field mask of IRQ mux, needed if different of 0xf.
47
48  st,package:
49    allOf:
50      - $ref: /schemas/types.yaml#/definitions/uint32
51      - enum: [1, 2, 4, 8]
52    description:
53     Indicates the SOC package used.
54     More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
55
56
57patternProperties:
58  '^gpio@[0-9a-f]*$':
59    type: object
60    properties:
61      gpio-controller: true
62      '#gpio-cells':
63        const: 2
64
65      reg:
66        maxItems: 1
67      clocks:
68        maxItems: 1
69      reset:
70        minItems: 1
71        maxItems: 1
72      gpio-ranges:
73        minItems: 1
74        maxItems: 16
75      ngpios:
76        description:
77          Number of available gpios in a bank.
78        minimum: 1
79        maximum: 16
80
81      st,bank-name:
82        allOf:
83          - $ref: "/schemas/types.yaml#/definitions/string"
84          - enum:
85            - GPIOA
86            - GPIOB
87            - GPIOC
88            - GPIOD
89            - GPIOE
90            - GPIOF
91            - GPIOG
92            - GPIOH
93            - GPIOI
94            - GPIOJ
95            - GPIOK
96            - GPIOZ
97        description:
98          Should be a name string for this bank as specified in the datasheet.
99
100      st,bank-ioport:
101        allOf:
102          - $ref: "/schemas/types.yaml#/definitions/uint32"
103          - minimum: 0
104          - maximum: 11
105
106        description:
107          Should correspond to the EXTI IOport selection (EXTI line used
108          to select GPIOs as interrupts).
109
110    required:
111      - gpio-controller
112      - '#gpio-cells'
113      - reg
114      - clocks
115      - st,bank-name
116
117  '-[0-9]*$':
118    type: object
119    patternProperties:
120      '^pins':
121        type: object
122        description: |
123          A pinctrl node should contain at least one subnode representing the
124          pinctrl group available on the machine. Each subnode will list the
125          pins it needs, and how they should be configured, with regard to muxer
126          configuration, pullups, drive, output high/low and output speed.
127        properties:
128          pinmux:
129            allOf:
130              - $ref: "/schemas/types.yaml#/definitions/uint32-array"
131            description: |
132              Integer array, represents gpio pin number and mux setting.
133              Supported pin number and mux varies for different SoCs, and are
134              defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
135              These defines are calculated as: ((port * 16 + line) << 8) | function
136              With:
137              - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
138              - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
139              - function: The function number, can be:
140              * 0 : GPIO
141              * 1 : Alternate Function 0
142              * 2 : Alternate Function 1
143              * 3 : Alternate Function 2
144              * ...
145              * 16 : Alternate Function 15
146              * 17 : Analog
147              To simplify the usage, macro is available to generate "pinmux" field.
148              This macro is available here:
149                - include/dt-bindings/pinctrl/stm32-pinfunc.h
150              Some examples of using macro:
151               /* GPIO A9 set as alernate function 2 */
152               ... {
153                          pinmux = <STM32_PINMUX('A', 9, AF2)>;
154               };
155               /* GPIO A9 set as GPIO  */
156               ... {
157                          pinmux = <STM32_PINMUX('A', 9, GPIO)>;
158               };
159               /* GPIO A9 set as analog */
160               ... {
161                          pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
162               };
163
164          bias-disable:
165            type: boolean
166          bias-pull-down:
167            type: boolean
168          bias-pull-up:
169            type: boolean
170          drive-push-pull:
171            type: boolean
172          drive-open-drain:
173            type: boolean
174          output-low:
175            type: boolean
176          output-high:
177            type: boolean
178          slew-rate:
179            description: |
180              0: Low speed
181              1: Medium speed
182              2: Fast speed
183              3: High speed
184            allOf:
185              - $ref: /schemas/types.yaml#/definitions/uint32
186              - enum: [0, 1, 2, 3]
187
188        required:
189          - pinmux
190
191required:
192  - compatible
193  - '#address-cells'
194  - '#size-cells'
195  - ranges
196  - pins-are-numbered
197
198examples:
199  - |
200    #include <dt-bindings/pinctrl/stm32-pinfunc.h>
201    #include <dt-bindings/mfd/stm32f4-rcc.h>
202    //Example 1
203      pinctrl@40020000 {
204              #address-cells = <1>;
205              #size-cells = <1>;
206              compatible = "st,stm32f429-pinctrl";
207              ranges = <0 0x40020000 0x3000>;
208              pins-are-numbered;
209
210              gpioa: gpio@0 {
211                      gpio-controller;
212                      #gpio-cells = <2>;
213                      reg = <0x0 0x400>;
214                      resets = <&reset_ahb1 0>;
215                      clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
216                      st,bank-name = "GPIOA";
217              };
218       };
219
220    //Example 2 (using gpio-ranges)
221      pinctrl@50020000 {
222              #address-cells = <1>;
223              #size-cells = <1>;
224              compatible = "st,stm32f429-pinctrl";
225              ranges = <0 0x50020000 0x3000>;
226              pins-are-numbered;
227
228              gpiob: gpio@1000 {
229                      gpio-controller;
230                      #gpio-cells = <2>;
231                      reg = <0x1000 0x400>;
232                      resets = <&reset_ahb1 0>;
233                      clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
234                      st,bank-name = "GPIOB";
235                      gpio-ranges = <&pinctrl 0 0 16>;
236              };
237
238              gpioc: gpio@2000 {
239                      gpio-controller;
240                      #gpio-cells = <2>;
241                      reg = <0x2000 0x400>;
242                      resets = <&reset_ahb1 0>;
243                      clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
244                      st,bank-name = "GPIOC";
245                      ngpios = <5>;
246                      gpio-ranges = <&pinctrl 0 16 3>,
247                                    <&pinctrl 14 30 2>;
248              };
249      };
250
251    //Example 3 pin groups
252      pinctrl@60020000 {
253        usart1_pins_a: usart1-0 {
254                pins1 {
255                        pinmux = <STM32_PINMUX('A', 9, AF7)>;
256                        bias-disable;
257                        drive-push-pull;
258                        slew-rate = <0>;
259                };
260                pins2 {
261                        pinmux = <STM32_PINMUX('A', 10, AF7)>;
262                        bias-disable;
263                };
264        };
265    };
266
267    usart1 {
268                pinctrl-0 = <&usart1_pins_a>;
269                pinctrl-names = "default";
270    };
271
272...
273