1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright (C) STMicroelectronics 2019.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: STM32 GPIO and Pin Mux/Config controller
9
10maintainers:
11  - Alexandre TORGUE <alexandre.torgue@foss.st.com>
12
13description: |
14  STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
15  controller. It controls the input/output settings on the available pins and
16  also provides ability to multiplex and configure the output of various
17  on-chip controllers onto these pads.
18
19properties:
20  compatible:
21    enum:
22      - st,stm32f429-pinctrl
23      - st,stm32f469-pinctrl
24      - st,stm32f746-pinctrl
25      - st,stm32f769-pinctrl
26      - st,stm32h743-pinctrl
27      - st,stm32mp135-pinctrl
28      - st,stm32mp157-pinctrl
29      - st,stm32mp157-z-pinctrl
30
31  '#address-cells':
32    const: 1
33  '#size-cells':
34    const: 1
35
36  ranges: true
37  pins-are-numbered:
38    $ref: /schemas/types.yaml#/definitions/flag
39    deprecated: true
40  hwlocks: true
41
42  interrupts:
43    maxItems: 1
44
45  st,syscfg:
46    description: Phandle+args to the syscon node which includes IRQ mux selection.
47    $ref: "/schemas/types.yaml#/definitions/phandle-array"
48    items:
49      - items:
50          - description: syscon node which includes IRQ mux selection
51          - description: The offset of the IRQ mux selection register
52          - description: The field mask of IRQ mux, needed if different of 0xf
53
54  st,package:
55    description:
56      Indicates the SOC package used.
57      More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
58    $ref: /schemas/types.yaml#/definitions/uint32
59    enum: [1, 2, 4, 8]
60
61patternProperties:
62  '^gpio@[0-9a-f]*$':
63    type: object
64    additionalProperties: false
65    properties:
66      gpio-controller: true
67      '#gpio-cells':
68        const: 2
69      interrupt-controller: true
70      '#interrupt-cells':
71        const: 2
72
73      reg:
74        maxItems: 1
75      clocks:
76        maxItems: 1
77      resets:
78        maxItems: 1
79      gpio-line-names: true
80      gpio-ranges:
81        minItems: 1
82        maxItems: 16
83      ngpios:
84        description:
85          Number of available gpios in a bank.
86        minimum: 1
87        maximum: 16
88
89      st,bank-name:
90        description:
91          Should be a name string for this bank as specified in the datasheet.
92        $ref: "/schemas/types.yaml#/definitions/string"
93        enum:
94          - GPIOA
95          - GPIOB
96          - GPIOC
97          - GPIOD
98          - GPIOE
99          - GPIOF
100          - GPIOG
101          - GPIOH
102          - GPIOI
103          - GPIOJ
104          - GPIOK
105          - GPIOZ
106
107      st,bank-ioport:
108        description:
109          Should correspond to the EXTI IOport selection (EXTI line used
110          to select GPIOs as interrupts).
111        $ref: "/schemas/types.yaml#/definitions/uint32"
112        minimum: 0
113        maximum: 11
114
115    patternProperties:
116      "^(.+-hog(-[0-9]+)?)$":
117        type: object
118        required:
119          - gpio-hog
120
121    required:
122      - gpio-controller
123      - '#gpio-cells'
124      - reg
125      - clocks
126      - st,bank-name
127
128  '-[0-9]*$':
129    type: object
130    additionalProperties: false
131
132    patternProperties:
133      '^pins':
134        type: object
135        additionalProperties: false
136        description: |
137          A pinctrl node should contain at least one subnode representing the
138          pinctrl group available on the machine. Each subnode will list the
139          pins it needs, and how they should be configured, with regard to muxer
140          configuration, pullups, drive, output high/low and output speed.
141        properties:
142          pinmux:
143            $ref: "/schemas/types.yaml#/definitions/uint32-array"
144            description: |
145              Integer array, represents gpio pin number and mux setting.
146              Supported pin number and mux varies for different SoCs, and are
147              defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
148              These defines are calculated as: ((port * 16 + line) << 8) | function
149              With:
150              - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
151              - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
152              - function: The function number, can be:
153              * 0 : GPIO
154              * 1 : Alternate Function 0
155              * 2 : Alternate Function 1
156              * 3 : Alternate Function 2
157              * ...
158              * 16 : Alternate Function 15
159              * 17 : Analog
160              To simplify the usage, macro is available to generate "pinmux" field.
161              This macro is available here:
162                - include/dt-bindings/pinctrl/stm32-pinfunc.h
163              Some examples of using macro:
164               /* GPIO A9 set as alernate function 2 */
165               ... {
166                          pinmux = <STM32_PINMUX('A', 9, AF2)>;
167               };
168               /* GPIO A9 set as GPIO  */
169               ... {
170                          pinmux = <STM32_PINMUX('A', 9, GPIO)>;
171               };
172               /* GPIO A9 set as analog */
173               ... {
174                          pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
175               };
176
177          bias-disable:
178            type: boolean
179          bias-pull-down:
180            type: boolean
181          bias-pull-up:
182            type: boolean
183          drive-push-pull:
184            type: boolean
185          drive-open-drain:
186            type: boolean
187          output-low:
188            type: boolean
189          output-high:
190            type: boolean
191          slew-rate:
192            description: |
193              0: Low speed
194              1: Medium speed
195              2: Fast speed
196              3: High speed
197            $ref: /schemas/types.yaml#/definitions/uint32
198            enum: [0, 1, 2, 3]
199
200        required:
201          - pinmux
202
203allOf:
204  - $ref: "pinctrl.yaml#"
205
206required:
207  - compatible
208  - '#address-cells'
209  - '#size-cells'
210  - ranges
211
212additionalProperties: false
213
214examples:
215  - |
216    #include <dt-bindings/pinctrl/stm32-pinfunc.h>
217    #include <dt-bindings/mfd/stm32f4-rcc.h>
218    //Example 1
219      pinctrl@40020000 {
220              #address-cells = <1>;
221              #size-cells = <1>;
222              compatible = "st,stm32f429-pinctrl";
223              ranges = <0 0x40020000 0x3000>;
224
225              gpioa: gpio@0 {
226                      gpio-controller;
227                      #gpio-cells = <2>;
228                      reg = <0x0 0x400>;
229                      resets = <&reset_ahb1 0>;
230                      clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
231                      st,bank-name = "GPIOA";
232              };
233       };
234
235    //Example 2 (using gpio-ranges)
236      pinctrl@50020000 {
237              #address-cells = <1>;
238              #size-cells = <1>;
239              compatible = "st,stm32f429-pinctrl";
240              ranges = <0 0x50020000 0x3000>;
241
242              gpiob: gpio@1000 {
243                      gpio-controller;
244                      #gpio-cells = <2>;
245                      reg = <0x1000 0x400>;
246                      resets = <&reset_ahb1 0>;
247                      clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
248                      st,bank-name = "GPIOB";
249                      gpio-ranges = <&pinctrl 0 0 16>;
250              };
251
252              gpioc: gpio@2000 {
253                      gpio-controller;
254                      #gpio-cells = <2>;
255                      reg = <0x2000 0x400>;
256                      resets = <&reset_ahb1 0>;
257                      clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
258                      st,bank-name = "GPIOC";
259                      ngpios = <5>;
260                      gpio-ranges = <&pinctrl 0 16 3>,
261                                    <&pinctrl 14 30 2>;
262              };
263      };
264
265    //Example 3 pin groups
266      pinctrl {
267        usart1_pins_a: usart1-0 {
268                pins1 {
269                        pinmux = <STM32_PINMUX('A', 9, AF7)>;
270                        bias-disable;
271                        drive-push-pull;
272                        slew-rate = <0>;
273                };
274                pins2 {
275                        pinmux = <STM32_PINMUX('A', 10, AF7)>;
276                        bias-disable;
277                };
278        };
279    };
280
281    usart1 {
282                pinctrl-0 = <&usart1_pins_a>;
283                pinctrl-names = "default";
284    };
285
286...
287