1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright (C) STMicroelectronics 2019.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: STM32 GPIO and Pin Mux/Config controller
9
10maintainers:
11  - Alexandre TORGUE <alexandre.torgue@st.com>
12
13description: |
14  STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
15  controller. It controls the input/output settings on the available pins and
16  also provides ability to multiplex and configure the output of various
17  on-chip controllers onto these pads.
18
19properties:
20  compatible:
21    enum:
22      - st,stm32f429-pinctrl
23      - st,stm32f469-pinctrl
24      - st,stm32f746-pinctrl
25      - st,stm32f769-pinctrl
26      - st,stm32h743-pinctrl
27      - st,stm32mp157-pinctrl
28      - st,stm32mp157-z-pinctrl
29
30  '#address-cells':
31    const: 1
32  '#size-cells':
33    const: 1
34
35  ranges: true
36  pins-are-numbered: true
37  hwlocks: true
38
39  interrupts:
40    maxItems: 1
41
42  st,syscfg:
43    allOf:
44      - $ref: "/schemas/types.yaml#/definitions/phandle-array"
45    description: Should be phandle/offset/mask
46      - Phandle to the syscon node which includes IRQ mux selection.
47      - The offset of the IRQ mux selection register.
48      - The field mask of IRQ mux, needed if different of 0xf.
49
50  st,package:
51    allOf:
52      - $ref: /schemas/types.yaml#/definitions/uint32
53      - enum: [1, 2, 4, 8]
54    description:
55     Indicates the SOC package used.
56     More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
57
58
59patternProperties:
60  '^gpio@[0-9a-f]*$':
61    type: object
62    properties:
63      gpio-controller: true
64      '#gpio-cells':
65        const: 2
66
67      reg:
68        maxItems: 1
69      clocks:
70        maxItems: 1
71      reset:
72        minItems: 1
73        maxItems: 1
74      gpio-ranges:
75        minItems: 1
76        maxItems: 16
77      ngpios:
78        description:
79          Number of available gpios in a bank.
80        minimum: 1
81        maximum: 16
82
83      st,bank-name:
84        allOf:
85          - $ref: "/schemas/types.yaml#/definitions/string"
86          - enum:
87            - GPIOA
88            - GPIOB
89            - GPIOC
90            - GPIOD
91            - GPIOE
92            - GPIOF
93            - GPIOG
94            - GPIOH
95            - GPIOI
96            - GPIOJ
97            - GPIOK
98            - GPIOZ
99        description:
100          Should be a name string for this bank as specified in the datasheet.
101
102      st,bank-ioport:
103        allOf:
104          - $ref: "/schemas/types.yaml#/definitions/uint32"
105          - minimum: 0
106          - maximum: 11
107
108        description:
109          Should correspond to the EXTI IOport selection (EXTI line used
110          to select GPIOs as interrupts).
111
112    required:
113      - gpio-controller
114      - '#gpio-cells'
115      - reg
116      - clocks
117      - st,bank-name
118
119  '-[0-9]*$':
120    type: object
121    patternProperties:
122      '^pins':
123        type: object
124        description: |
125          A pinctrl node should contain at least one subnode representing the
126          pinctrl group available on the machine. Each subnode will list the
127          pins it needs, and how they should be configured, with regard to muxer
128          configuration, pullups, drive, output high/low and output speed.
129        properties:
130          pinmux:
131            allOf:
132              - $ref: "/schemas/types.yaml#/definitions/uint32-array"
133            description: |
134              Integer array, represents gpio pin number and mux setting.
135              Supported pin number and mux varies for different SoCs, and are
136              defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
137              These defines are calculated as: ((port * 16 + line) << 8) | function
138              With:
139              - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
140              - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
141              - function: The function number, can be:
142              * 0 : GPIO
143              * 1 : Alternate Function 0
144              * 2 : Alternate Function 1
145              * 3 : Alternate Function 2
146              * ...
147              * 16 : Alternate Function 15
148              * 17 : Analog
149              To simplify the usage, macro is available to generate "pinmux" field.
150              This macro is available here:
151                - include/dt-bindings/pinctrl/stm32-pinfunc.h
152              Some examples of using macro:
153               /* GPIO A9 set as alernate function 2 */
154               ... {
155                          pinmux = <STM32_PINMUX('A', 9, AF2)>;
156               };
157               /* GPIO A9 set as GPIO  */
158               ... {
159                          pinmux = <STM32_PINMUX('A', 9, GPIO)>;
160               };
161               /* GPIO A9 set as analog */
162               ... {
163                          pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
164               };
165
166          bias-disable:
167            type: boolean
168          bias-pull-down:
169            type: boolean
170          bias-pull-up:
171            type: boolean
172          drive-push-pull:
173            type: boolean
174          drive-open-drain:
175            type: boolean
176          output-low:
177            type: boolean
178          output-high:
179            type: boolean
180          slew-rate:
181            description: |
182              0: Low speed
183              1: Medium speed
184              2: Fast speed
185              3: High speed
186            allOf:
187              - $ref: /schemas/types.yaml#/definitions/uint32
188              - enum: [0, 1, 2, 3]
189
190        required:
191          - pinmux
192
193required:
194  - compatible
195  - '#address-cells'
196  - '#size-cells'
197  - ranges
198  - pins-are-numbered
199
200additionalProperties: false
201
202examples:
203  - |
204    #include <dt-bindings/pinctrl/stm32-pinfunc.h>
205    #include <dt-bindings/mfd/stm32f4-rcc.h>
206    //Example 1
207      pinctrl@40020000 {
208              #address-cells = <1>;
209              #size-cells = <1>;
210              compatible = "st,stm32f429-pinctrl";
211              ranges = <0 0x40020000 0x3000>;
212              pins-are-numbered;
213
214              gpioa: gpio@0 {
215                      gpio-controller;
216                      #gpio-cells = <2>;
217                      reg = <0x0 0x400>;
218                      resets = <&reset_ahb1 0>;
219                      clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
220                      st,bank-name = "GPIOA";
221              };
222       };
223
224    //Example 2 (using gpio-ranges)
225      pinctrl@50020000 {
226              #address-cells = <1>;
227              #size-cells = <1>;
228              compatible = "st,stm32f429-pinctrl";
229              ranges = <0 0x50020000 0x3000>;
230              pins-are-numbered;
231
232              gpiob: gpio@1000 {
233                      gpio-controller;
234                      #gpio-cells = <2>;
235                      reg = <0x1000 0x400>;
236                      resets = <&reset_ahb1 0>;
237                      clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
238                      st,bank-name = "GPIOB";
239                      gpio-ranges = <&pinctrl 0 0 16>;
240              };
241
242              gpioc: gpio@2000 {
243                      gpio-controller;
244                      #gpio-cells = <2>;
245                      reg = <0x2000 0x400>;
246                      resets = <&reset_ahb1 0>;
247                      clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
248                      st,bank-name = "GPIOC";
249                      ngpios = <5>;
250                      gpio-ranges = <&pinctrl 0 16 3>,
251                                    <&pinctrl 14 30 2>;
252              };
253      };
254
255    //Example 3 pin groups
256      pinctrl {
257        usart1_pins_a: usart1-0 {
258                pins1 {
259                        pinmux = <STM32_PINMUX('A', 9, AF7)>;
260                        bias-disable;
261                        drive-push-pull;
262                        slew-rate = <0>;
263                };
264                pins2 {
265                        pinmux = <STM32_PINMUX('A', 10, AF7)>;
266                        bias-disable;
267                };
268        };
269    };
270
271    usart1 {
272                pinctrl-0 = <&usart1_pins_a>;
273                pinctrl-names = "default";
274    };
275
276...
277