1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright (C) STMicroelectronics 2019.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: STM32 GPIO and Pin Mux/Config controller
9
10maintainers:
11  - Alexandre TORGUE <alexandre.torgue@st.com>
12
13description: |
14  STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
15  controller. It controls the input/output settings on the available pins and
16  also provides ability to multiplex and configure the output of various
17  on-chip controllers onto these pads.
18
19properties:
20  compatible:
21    enum:
22      - st,stm32f429-pinctrl
23      - st,stm32f469-pinctrl
24      - st,stm32f746-pinctrl
25      - st,stm32f769-pinctrl
26      - st,stm32h743-pinctrl
27      - st,stm32mp157-pinctrl
28      - st,stm32mp157-z-pinctrl
29
30  '#address-cells':
31    const: 1
32  '#size-cells':
33    const: 1
34
35  ranges: true
36  pins-are-numbered: true
37  hwlocks: true
38
39  st,syscfg:
40    allOf:
41      - $ref: "/schemas/types.yaml#/definitions/phandle-array"
42    description: Should be phandle/offset/mask
43      - Phandle to the syscon node which includes IRQ mux selection.
44      - The offset of the IRQ mux selection register.
45      - The field mask of IRQ mux, needed if different of 0xf.
46
47  st,package:
48    allOf:
49      - $ref: /schemas/types.yaml#/definitions/uint32
50      - enum: [1, 2, 4, 8]
51    description:
52     Indicates the SOC package used.
53     More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
54
55
56patternProperties:
57  '^gpio@[0-9a-f]*$':
58    type: object
59    properties:
60      gpio-controller: true
61      '#gpio-cells':
62        const: 2
63
64      reg:
65        maxItems: 1
66      clocks:
67        maxItems: 1
68      reset:
69        minItems: 1
70        maxItems: 1
71      gpio-ranges:
72        minItems: 1
73        maxItems: 16
74      ngpios:
75        description:
76          Number of available gpios in a bank.
77        minimum: 1
78        maximum: 16
79
80      st,bank-name:
81        allOf:
82          - $ref: "/schemas/types.yaml#/definitions/string"
83          - enum:
84            - GPIOA
85            - GPIOB
86            - GPIOC
87            - GPIOD
88            - GPIOE
89            - GPIOF
90            - GPIOG
91            - GPIOH
92            - GPIOI
93            - GPIOJ
94            - GPIOK
95            - GPIOZ
96        description:
97          Should be a name string for this bank as specified in the datasheet.
98
99      st,bank-ioport:
100        allOf:
101          - $ref: "/schemas/types.yaml#/definitions/uint32"
102          - minimum: 0
103          - maximum: 11
104
105        description:
106          Should correspond to the EXTI IOport selection (EXTI line used
107          to select GPIOs as interrupts).
108
109    required:
110      - gpio-controller
111      - '#gpio-cells'
112      - reg
113      - clocks
114      - st,bank-name
115
116  '-[0-9]*$':
117    type: object
118    patternProperties:
119      '^pins':
120        type: object
121        description: |
122          A pinctrl node should contain at least one subnode representing the
123          pinctrl group available on the machine. Each subnode will list the
124          pins it needs, and how they should be configured, with regard to muxer
125          configuration, pullups, drive, output high/low and output speed.
126        properties:
127          pinmux:
128            allOf:
129              - $ref: "/schemas/types.yaml#/definitions/uint32-array"
130            description: |
131              Integer array, represents gpio pin number and mux setting.
132              Supported pin number and mux varies for different SoCs, and are
133              defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
134              These defines are calculated as: ((port * 16 + line) << 8) | function
135              With:
136              - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
137              - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
138              - function: The function number, can be:
139              * 0 : GPIO
140              * 1 : Alternate Function 0
141              * 2 : Alternate Function 1
142              * 3 : Alternate Function 2
143              * ...
144              * 16 : Alternate Function 15
145              * 17 : Analog
146              To simplify the usage, macro is available to generate "pinmux" field.
147              This macro is available here:
148                - include/dt-bindings/pinctrl/stm32-pinfunc.h
149              Some examples of using macro:
150               /* GPIO A9 set as alernate function 2 */
151               ... {
152                          pinmux = <STM32_PINMUX('A', 9, AF2)>;
153               };
154               /* GPIO A9 set as GPIO  */
155               ... {
156                          pinmux = <STM32_PINMUX('A', 9, GPIO)>;
157               };
158               /* GPIO A9 set as analog */
159               ... {
160                          pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
161               };
162
163          bias-disable:
164            type: boolean
165          bias-pull-down:
166            type: boolean
167          bias-pull-up:
168            type: boolean
169          drive-push-pull:
170            type: boolean
171          drive-open-drain:
172            type: boolean
173          output-low:
174            type: boolean
175          output-high:
176            type: boolean
177          slew-rate:
178            description: |
179              0: Low speed
180              1: Medium speed
181              2: Fast speed
182              3: High speed
183            allOf:
184              - $ref: /schemas/types.yaml#/definitions/uint32
185              - enum: [0, 1, 2, 3]
186
187        required:
188          - pinmux
189
190required:
191  - compatible
192  - '#address-cells'
193  - '#size-cells'
194  - ranges
195  - pins-are-numbered
196
197additionalProperties: false
198
199examples:
200  - |
201    #include <dt-bindings/pinctrl/stm32-pinfunc.h>
202    #include <dt-bindings/mfd/stm32f4-rcc.h>
203    //Example 1
204      pinctrl@40020000 {
205              #address-cells = <1>;
206              #size-cells = <1>;
207              compatible = "st,stm32f429-pinctrl";
208              ranges = <0 0x40020000 0x3000>;
209              pins-are-numbered;
210
211              gpioa: gpio@0 {
212                      gpio-controller;
213                      #gpio-cells = <2>;
214                      reg = <0x0 0x400>;
215                      resets = <&reset_ahb1 0>;
216                      clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
217                      st,bank-name = "GPIOA";
218              };
219       };
220
221    //Example 2 (using gpio-ranges)
222      pinctrl@50020000 {
223              #address-cells = <1>;
224              #size-cells = <1>;
225              compatible = "st,stm32f429-pinctrl";
226              ranges = <0 0x50020000 0x3000>;
227              pins-are-numbered;
228
229              gpiob: gpio@1000 {
230                      gpio-controller;
231                      #gpio-cells = <2>;
232                      reg = <0x1000 0x400>;
233                      resets = <&reset_ahb1 0>;
234                      clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
235                      st,bank-name = "GPIOB";
236                      gpio-ranges = <&pinctrl 0 0 16>;
237              };
238
239              gpioc: gpio@2000 {
240                      gpio-controller;
241                      #gpio-cells = <2>;
242                      reg = <0x2000 0x400>;
243                      resets = <&reset_ahb1 0>;
244                      clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
245                      st,bank-name = "GPIOC";
246                      ngpios = <5>;
247                      gpio-ranges = <&pinctrl 0 16 3>,
248                                    <&pinctrl 14 30 2>;
249              };
250      };
251
252    //Example 3 pin groups
253      pinctrl {
254        usart1_pins_a: usart1-0 {
255                pins1 {
256                        pinmux = <STM32_PINMUX('A', 9, AF7)>;
257                        bias-disable;
258                        drive-push-pull;
259                        slew-rate = <0>;
260                };
261                pins2 {
262                        pinmux = <STM32_PINMUX('A', 10, AF7)>;
263                        bias-disable;
264                };
265        };
266    };
267
268    usart1 {
269                pinctrl-0 = <&usart1_pins_a>;
270                pinctrl-names = "default";
271    };
272
273...
274