1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2# Copyright (C) STMicroelectronics 2019. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: STM32 GPIO and Pin Mux/Config controller 9 10maintainers: 11 - Alexandre TORGUE <alexandre.torgue@st.com> 12 13description: | 14 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware 15 controller. It controls the input/output settings on the available pins and 16 also provides ability to multiplex and configure the output of various 17 on-chip controllers onto these pads. 18 19properties: 20 compatible: 21 enum: 22 - st,stm32f429-pinctrl 23 - st,stm32f469-pinctrl 24 - st,stm32f746-pinctrl 25 - st,stm32f769-pinctrl 26 - st,stm32h743-pinctrl 27 - st,stm32mp157-pinctrl 28 - st,stm32mp157-z-pinctrl 29 30 '#address-cells': 31 const: 1 32 '#size-cells': 33 const: 1 34 35 ranges: true 36 pins-are-numbered: true 37 hwlocks: true 38 39 st,syscfg: 40 description: Should be phandle/offset/mask 41 - Phandle to the syscon node which includes IRQ mux selection. 42 - The offset of the IRQ mux selection register. 43 - The field mask of IRQ mux, needed if different of 0xf. 44 $ref: "/schemas/types.yaml#/definitions/phandle-array" 45 46 st,package: 47 description: 48 Indicates the SOC package used. 49 More details in include/dt-bindings/pinctrl/stm32-pinfunc.h 50 $ref: /schemas/types.yaml#/definitions/uint32 51 enum: [1, 2, 4, 8] 52 53patternProperties: 54 '^gpio@[0-9a-f]*$': 55 type: object 56 properties: 57 gpio-controller: true 58 '#gpio-cells': 59 const: 2 60 61 reg: 62 maxItems: 1 63 clocks: 64 maxItems: 1 65 reset: 66 minItems: 1 67 maxItems: 1 68 gpio-ranges: 69 minItems: 1 70 maxItems: 16 71 ngpios: 72 description: 73 Number of available gpios in a bank. 74 minimum: 1 75 maximum: 16 76 77 st,bank-name: 78 description: 79 Should be a name string for this bank as specified in the datasheet. 80 $ref: "/schemas/types.yaml#/definitions/string" 81 enum: 82 - GPIOA 83 - GPIOB 84 - GPIOC 85 - GPIOD 86 - GPIOE 87 - GPIOF 88 - GPIOG 89 - GPIOH 90 - GPIOI 91 - GPIOJ 92 - GPIOK 93 - GPIOZ 94 95 st,bank-ioport: 96 description: 97 Should correspond to the EXTI IOport selection (EXTI line used 98 to select GPIOs as interrupts). 99 $ref: "/schemas/types.yaml#/definitions/uint32" 100 minimum: 0 101 maximum: 11 102 103 required: 104 - gpio-controller 105 - '#gpio-cells' 106 - reg 107 - clocks 108 - st,bank-name 109 110 '-[0-9]*$': 111 type: object 112 patternProperties: 113 '^pins': 114 type: object 115 description: | 116 A pinctrl node should contain at least one subnode representing the 117 pinctrl group available on the machine. Each subnode will list the 118 pins it needs, and how they should be configured, with regard to muxer 119 configuration, pullups, drive, output high/low and output speed. 120 properties: 121 pinmux: 122 $ref: "/schemas/types.yaml#/definitions/uint32-array" 123 description: | 124 Integer array, represents gpio pin number and mux setting. 125 Supported pin number and mux varies for different SoCs, and are 126 defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly. 127 These defines are calculated as: ((port * 16 + line) << 8) | function 128 With: 129 - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11) 130 - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15) 131 - function: The function number, can be: 132 * 0 : GPIO 133 * 1 : Alternate Function 0 134 * 2 : Alternate Function 1 135 * 3 : Alternate Function 2 136 * ... 137 * 16 : Alternate Function 15 138 * 17 : Analog 139 To simplify the usage, macro is available to generate "pinmux" field. 140 This macro is available here: 141 - include/dt-bindings/pinctrl/stm32-pinfunc.h 142 Some examples of using macro: 143 /* GPIO A9 set as alernate function 2 */ 144 ... { 145 pinmux = <STM32_PINMUX('A', 9, AF2)>; 146 }; 147 /* GPIO A9 set as GPIO */ 148 ... { 149 pinmux = <STM32_PINMUX('A', 9, GPIO)>; 150 }; 151 /* GPIO A9 set as analog */ 152 ... { 153 pinmux = <STM32_PINMUX('A', 9, ANALOG)>; 154 }; 155 156 bias-disable: 157 type: boolean 158 bias-pull-down: 159 type: boolean 160 bias-pull-up: 161 type: boolean 162 drive-push-pull: 163 type: boolean 164 drive-open-drain: 165 type: boolean 166 output-low: 167 type: boolean 168 output-high: 169 type: boolean 170 slew-rate: 171 description: | 172 0: Low speed 173 1: Medium speed 174 2: Fast speed 175 3: High speed 176 $ref: /schemas/types.yaml#/definitions/uint32 177 enum: [0, 1, 2, 3] 178 179 required: 180 - pinmux 181 182required: 183 - compatible 184 - '#address-cells' 185 - '#size-cells' 186 - ranges 187 - pins-are-numbered 188 189additionalProperties: false 190 191examples: 192 - | 193 #include <dt-bindings/pinctrl/stm32-pinfunc.h> 194 #include <dt-bindings/mfd/stm32f4-rcc.h> 195 //Example 1 196 pinctrl@40020000 { 197 #address-cells = <1>; 198 #size-cells = <1>; 199 compatible = "st,stm32f429-pinctrl"; 200 ranges = <0 0x40020000 0x3000>; 201 pins-are-numbered; 202 203 gpioa: gpio@0 { 204 gpio-controller; 205 #gpio-cells = <2>; 206 reg = <0x0 0x400>; 207 resets = <&reset_ahb1 0>; 208 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>; 209 st,bank-name = "GPIOA"; 210 }; 211 }; 212 213 //Example 2 (using gpio-ranges) 214 pinctrl@50020000 { 215 #address-cells = <1>; 216 #size-cells = <1>; 217 compatible = "st,stm32f429-pinctrl"; 218 ranges = <0 0x50020000 0x3000>; 219 pins-are-numbered; 220 221 gpiob: gpio@1000 { 222 gpio-controller; 223 #gpio-cells = <2>; 224 reg = <0x1000 0x400>; 225 resets = <&reset_ahb1 0>; 226 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>; 227 st,bank-name = "GPIOB"; 228 gpio-ranges = <&pinctrl 0 0 16>; 229 }; 230 231 gpioc: gpio@2000 { 232 gpio-controller; 233 #gpio-cells = <2>; 234 reg = <0x2000 0x400>; 235 resets = <&reset_ahb1 0>; 236 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>; 237 st,bank-name = "GPIOC"; 238 ngpios = <5>; 239 gpio-ranges = <&pinctrl 0 16 3>, 240 <&pinctrl 14 30 2>; 241 }; 242 }; 243 244 //Example 3 pin groups 245 pinctrl { 246 usart1_pins_a: usart1-0 { 247 pins1 { 248 pinmux = <STM32_PINMUX('A', 9, AF7)>; 249 bias-disable; 250 drive-push-pull; 251 slew-rate = <0>; 252 }; 253 pins2 { 254 pinmux = <STM32_PINMUX('A', 10, AF7)>; 255 bias-disable; 256 }; 257 }; 258 }; 259 260 usart1 { 261 pinctrl-0 = <&usart1_pins_a>; 262 pinctrl-names = "default"; 263 }; 264 265... 266