1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright (C) STMicroelectronics 2019.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: STM32 GPIO and Pin Mux/Config controller
9
10maintainers:
11  - Alexandre TORGUE <alexandre.torgue@st.com>
12
13description: |
14  STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
15  controller. It controls the input/output settings on the available pins and
16  also provides ability to multiplex and configure the output of various
17  on-chip controllers onto these pads.
18
19properties:
20  compatible:
21    enum:
22      - st,stm32f429-pinctrl
23      - st,stm32f469-pinctrl
24      - st,stm32f746-pinctrl
25      - st,stm32f769-pinctrl
26      - st,stm32h743-pinctrl
27      - st,stm32mp157-pinctrl
28      - st,stm32mp157-z-pinctrl
29
30  '#address-cells':
31    const: 1
32  '#size-cells':
33    const: 1
34
35  ranges: true
36  pins-are-numbered: true
37  hwlocks: true
38
39  st,syscfg:
40    $ref: "/schemas/types.yaml#/definitions/phandle-array"
41    description: Should be phandle/offset/mask
42    items:
43      - description: Phandle to the syscon node which includes IRQ mux selection.
44      - description: The offset of the IRQ mux selection register.
45      - description: The field mask of IRQ mux, needed if different of 0xf.
46
47  st,package:
48    allOf:
49      - $ref: /schemas/types.yaml#/definitions/uint32
50      - enum: [1, 2, 4, 8]
51    description:
52     Indicates the SOC package used.
53     More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
54
55
56patternProperties:
57  '^gpio@[0-9a-f]*$':
58    properties:
59      gpio-controller: true
60      '#gpio-cells':
61        const: 2
62
63      reg:
64        maxItems: 1
65      clocks:
66        maxItems: 1
67      reset:
68        minItems: 1
69        maxItems: 1
70      gpio-ranges:
71        minItems: 1
72        maxItems: 16
73      ngpios:
74        description:
75          Number of available gpios in a bank.
76        minimum: 1
77        maximum: 16
78
79      st,bank-name:
80        allOf:
81          - $ref: "/schemas/types.yaml#/definitions/string"
82          - enum:
83            - GPIOA
84            - GPIOB
85            - GPIOC
86            - GPIOD
87            - GPIOE
88            - GPIOF
89            - GPIOG
90            - GPIOH
91            - GPIOI
92            - GPIOJ
93            - GPIOK
94            - GPIOZ
95        description:
96          Should be a name string for this bank as specified in the datasheet.
97
98      st,bank-ioport:
99        allOf:
100          - $ref: "/schemas/types.yaml#/definitions/uint32"
101          - minimum: 0
102          - maximum: 11
103
104        description:
105          Should correspond to the EXTI IOport selection (EXTI line used
106          to select GPIOs as interrupts).
107
108    required:
109      - gpio-controller
110      - '#gpio-cells'
111      - reg
112      - clocks
113      - st,bank-name
114
115  '-[0-9]*$':
116    patternProperties:
117      '^pins':
118        description: |
119          A pinctrl node should contain at least one subnode representing the
120          pinctrl group available on the machine. Each subnode will list the
121          pins it needs, and how they should be configured, with regard to muxer
122          configuration, pullups, drive, output high/low and output speed.
123        properties:
124          pinmux:
125            allOf:
126              - $ref: "/schemas/types.yaml#/definitions/uint32-array"
127            description: |
128              Integer array, represents gpio pin number and mux setting.
129              Supported pin number and mux varies for different SoCs, and are
130              defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
131              These defines are calculated as: ((port * 16 + line) << 8) | function
132              With:
133              - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
134              - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
135              - function: The function number, can be:
136              * 0 : GPIO
137              * 1 : Alternate Function 0
138              * 2 : Alternate Function 1
139              * 3 : Alternate Function 2
140              * ...
141              * 16 : Alternate Function 15
142              * 17 : Analog
143              To simplify the usage, macro is available to generate "pinmux" field.
144              This macro is available here:
145                - include/dt-bindings/pinctrl/stm32-pinfunc.h
146              Some examples of using macro:
147               /* GPIO A9 set as alernate function 2 */
148               ... {
149                          pinmux = <STM32_PINMUX('A', 9, AF2)>;
150               };
151               /* GPIO A9 set as GPIO  */
152               ... {
153                          pinmux = <STM32_PINMUX('A', 9, GPIO)>;
154               };
155               /* GPIO A9 set as analog */
156               ... {
157                          pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
158               };
159
160          bias-disable:
161            type: boolean
162          bias-pull-down:
163            type: boolean
164          bias-pull-up:
165            type: boolean
166          drive-push-pull:
167            type: boolean
168          drive-open-drain:
169            type: boolean
170          output-low:
171            type: boolean
172          output-high:
173            type: boolean
174          slew-rate:
175            description: |
176              0: Low speed
177              1: Medium speed
178              2: Fast speed
179              3: High speed
180            allOf:
181              - $ref: /schemas/types.yaml#/definitions/uint32
182              - enum: [0, 1, 2, 3]
183
184        required:
185          - pinmux
186
187required:
188  - compatible
189  - '#address-cells'
190  - '#size-cells'
191  - ranges
192  - pins-are-numbered
193
194examples:
195  - |
196    #include <dt-bindings/pinctrl/stm32-pinfunc.h>
197    //Example 1
198      pinctrl@40020000 {
199              #address-cells = <1>;
200              #size-cells = <1>;
201              compatible = "st,stm32f429-pinctrl";
202              ranges = <0 0x40020000 0x3000>;
203              pins-are-numbered;
204
205              gpioa: gpio@0 {
206                      gpio-controller;
207                      #gpio-cells = <2>;
208                      reg = <0x0 0x400>;
209                      resets = <&reset_ahb1 0>;
210                      st,bank-name = "GPIOA";
211              };
212       };
213
214    //Example 2 (using gpio-ranges)
215      pinctrl@50020000 {
216              #address-cells = <1>;
217              #size-cells = <1>;
218              compatible = "st,stm32f429-pinctrl";
219              ranges = <0 0x50020000 0x3000>;
220              pins-are-numbered;
221
222              gpiob: gpio@1000 {
223                      gpio-controller;
224                      #gpio-cells = <2>;
225                      reg = <0x1000 0x400>;
226                      resets = <&reset_ahb1 0>;
227                      st,bank-name = "GPIOB";
228                      gpio-ranges = <&pinctrl 0 0 16>;
229              };
230
231              gpioc: gpio@2000 {
232                      gpio-controller;
233                      #gpio-cells = <2>;
234                      reg = <0x2000 0x400>;
235                      resets = <&reset_ahb1 0>;
236                      st,bank-name = "GPIOC";
237                      ngpios = <5>;
238                      gpio-ranges = <&pinctrl 0 16 3>,
239                                    <&pinctrl 14 30 2>;
240              };
241      };
242
243    //Example 3 pin groups
244      pinctrl@60020000 {
245        usart1_pins_a: usart1-0 {
246                pins1 {
247                        pinmux = <STM32_PINMUX('A', 9, AF7)>;
248                        bias-disable;
249                        drive-push-pull;
250                        slew-rate = <0>;
251                };
252                pins2 {
253                        pinmux = <STM32_PINMUX('A', 10, AF7)>;
254                        bias-disable;
255                };
256        };
257    };
258
259    usart1 {
260                pinctrl-0 = <&usart1_pins_a>;
261                pinctrl-names = "default";
262    };
263
264...
265