1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/rockchip,pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip Pinmux Controller
8
9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12description: |
13  The Rockchip Pinmux Controller enables the IC to share one PAD
14  to several functional blocks. The sharing is done by multiplexing
15  the PAD input/output signals. For each PAD there are several muxing
16  options with option 0 being used as a GPIO.
17
18  Please refer to pinctrl-bindings.txt in this directory for details of the
19  common pinctrl bindings used by client devices, including the meaning of the
20  phrase "pin configuration node".
21
22  The Rockchip pin configuration node is a node of a group of pins which can be
23  used for a specific device or function. This node represents both mux and
24  config of the pins in that group. The 'pins' selects the function mode
25  (also named pin mode) this pin can work on and the 'config' configures
26  various pad settings such as pull-up, etc.
27
28  The pins are grouped into up to 9 individual pin banks which need to be
29  defined as gpio sub-nodes of the pinmux controller.
30
31properties:
32  compatible:
33    enum:
34      - rockchip,px30-pinctrl
35      - rockchip,rk2928-pinctrl
36      - rockchip,rk3066a-pinctrl
37      - rockchip,rk3066b-pinctrl
38      - rockchip,rk3128-pinctrl
39      - rockchip,rk3188-pinctrl
40      - rockchip,rk3228-pinctrl
41      - rockchip,rk3288-pinctrl
42      - rockchip,rk3308-pinctrl
43      - rockchip,rk3328-pinctrl
44      - rockchip,rk3368-pinctrl
45      - rockchip,rk3399-pinctrl
46      - rockchip,rk3568-pinctrl
47      - rockchip,rv1108-pinctrl
48
49  rockchip,grf:
50    $ref: "/schemas/types.yaml#/definitions/phandle"
51    description:
52      The phandle of the syscon node for the GRF registers.
53
54  rockchip,pmu:
55    $ref: "/schemas/types.yaml#/definitions/phandle"
56    description:
57      The phandle of the syscon node for the PMU registers,
58      as some SoCs carry parts of the iomux controller registers there.
59      Required for at least rk3188 and rk3288. On the rk3368 this should
60      point to the PMUGRF syscon.
61
62  "#address-cells":
63    enum: [1, 2]
64
65  "#size-cells":
66    enum: [1, 2]
67
68  ranges: true
69
70required:
71  - compatible
72  - rockchip,grf
73  - "#address-cells"
74  - "#size-cells"
75  - ranges
76
77patternProperties:
78  "gpio@[0-9a-f]+$":
79    type: object
80
81    $ref: "/schemas/gpio/rockchip,gpio-bank.yaml#"
82
83    unevaluatedProperties: false
84
85  "pcfg-[a-z0-9-]+$":
86    type: object
87    properties:
88      bias-disable: true
89
90      bias-pull-down: true
91
92      bias-pull-pin-default: true
93
94      bias-pull-up: true
95
96      drive-strength:
97        minimum: 0
98        maximum: 20
99
100      input-enable: true
101
102      input-schmitt-enable: true
103
104      output-high: true
105
106      output-low: true
107
108    additionalProperties: false
109
110additionalProperties:
111  type: object
112  additionalProperties:
113    type: object
114    properties:
115      rockchip,pins:
116        $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
117        minItems: 1
118        items:
119          items:
120            - minimum: 0
121              maximum: 8
122              description:
123                Pin bank.
124            - minimum: 0
125              maximum: 31
126              description:
127                Pin bank index.
128            - minimum: 0
129              maximum: 6
130              description:
131                Mux 0 means GPIO and mux 1 to N means
132                the specific device function.
133            - description:
134                The phandle of a node contains the generic pinconfig options
135                to use as described in pinctrl-bindings.txt.
136
137examples:
138  - |
139    #include <dt-bindings/interrupt-controller/arm-gic.h>
140    #include <dt-bindings/pinctrl/rockchip.h>
141
142    pinctrl: pinctrl {
143      compatible = "rockchip,rk3066a-pinctrl";
144      rockchip,grf = <&grf>;
145
146      #address-cells = <1>;
147      #size-cells = <1>;
148      ranges;
149
150      gpio0: gpio@20034000 {
151        compatible = "rockchip,gpio-bank";
152        reg = <0x20034000 0x100>;
153        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
154        clocks = <&clk_gates8 9>;
155
156        gpio-controller;
157        #gpio-cells = <2>;
158
159        interrupt-controller;
160        #interrupt-cells = <2>;
161      };
162
163      pcfg_pull_default: pcfg-pull-default {
164        bias-pull-pin-default;
165      };
166
167      uart2 {
168        uart2_xfer: uart2-xfer {
169          rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
170                          <1 RK_PB1 1 &pcfg_pull_default>;
171        };
172      };
173    };
174
175    uart2: serial@20064000 {
176      compatible = "snps,dw-apb-uart";
177      reg = <0x20064000 0x400>;
178      interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
179      clocks = <&mux_uart2>;
180      pinctrl-0 = <&uart2_xfer>;
181      pinctrl-names = "default";
182      reg-io-width = <1>;
183      reg-shift = <2>;
184    };
185