1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/renesas,rzv2m-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/V2M combined Pin and GPIO controller
8
9maintainers:
10  - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11  - Geert Uytterhoeven <geert+renesas@glider.be>
12
13description:
14  The Renesas RZ/V2M SoC features a combined Pin and GPIO controller.
15  Pin multiplexing and GPIO configuration is performed on a per-pin basis.
16  Each port features up to 16 pins, each of them configurable for GPIO function
17  (port mode) or in alternate function mode.
18  Up to 8 different alternate function modes exist for each single pin.
19
20properties:
21  compatible:
22    const: renesas,r9a09g011-pinctrl # RZ/V2M
23
24  reg:
25    maxItems: 1
26
27  gpio-controller: true
28
29  '#gpio-cells':
30    const: 2
31    description:
32      The first cell contains the global GPIO port index, constructed using the
33      RZV2M_GPIO() helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h> and the
34      second cell represents consumer flag as mentioned in ../gpio/gpio.txt
35      E.g. "RZV2M_GPIO(8, 1)" for P8_1.
36
37  gpio-ranges:
38    maxItems: 1
39
40  interrupts:
41    description: INEXINT[0..38] corresponding to individual pin inputs.
42    maxItems: 39
43
44  clocks:
45    maxItems: 1
46
47  power-domains:
48    maxItems: 1
49
50  resets:
51    maxItems: 1
52
53additionalProperties:
54  anyOf:
55    - type: object
56      allOf:
57        - $ref: pincfg-node.yaml#
58        - $ref: pinmux-node.yaml#
59
60      description:
61        Pin controller client devices use pin configuration subnodes (children
62        and grandchildren) for desired pin configuration.
63        Client device subnodes use below standard properties.
64
65      properties:
66        pinmux:
67          description:
68            Values are constructed from GPIO port number, pin number, and
69            alternate function configuration number using the RZV2M_PORT_PINMUX()
70            helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h>.
71        pins: true
72        bias-disable: true
73        bias-pull-down: true
74        bias-pull-up: true
75        drive-strength-microamp:
76          # Superset of supported values
77          enum: [ 1600, 1800, 2000, 3200, 3800, 4000, 6400, 7800, 8000,
78                  9000, 9600, 11000, 12000, 13000, 18000 ]
79        slew-rate:
80          description: 0 is slow slew rate, 1 is fast slew rate
81          enum: [ 0, 1 ]
82        gpio-hog: true
83        gpios: true
84        output-high: true
85        output-low: true
86        line-name: true
87
88    - type: object
89      additionalProperties:
90        $ref: "#/additionalProperties/anyOf/0"
91
92allOf:
93  - $ref: pinctrl.yaml#
94
95required:
96  - compatible
97  - reg
98  - gpio-controller
99  - '#gpio-cells'
100  - gpio-ranges
101  - interrupts
102  - clocks
103  - power-domains
104  - resets
105
106examples:
107  - |
108    #include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
109    #include <dt-bindings/clock/r9a09g011-cpg.h>
110    #include <dt-bindings/interrupt-controller/arm-gic.h>
111
112    pinctrl: pinctrl@b6250000 {
113            compatible = "renesas,r9a09g011-pinctrl";
114            reg = <0xb6250000 0x800>;
115
116            gpio-controller;
117            #gpio-cells = <2>;
118            gpio-ranges = <&pinctrl 0 0 352>;
119            interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
120                         <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
121                         <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
122                         <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
123                         <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
124                         <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
125                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
126                         <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
127                         <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
128                         <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
129                         <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
130                         <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
131                         <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
132                         <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
133                         <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
134                         <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
135                         <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
136                         <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
137                         <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
138                         <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
139                         <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
140                         <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
141                         <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
142                         <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
143                         <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
144                         <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
145                         <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
146                         <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
147                         <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
148                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
149                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
150                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
151                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
152                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
153                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
154                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
155                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
156                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
157                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
158            clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>;
159            resets = <&cpg R9A09G011_PFC_PRESETN>;
160            power-domains = <&cpg>;
161
162            i2c2_pins: i2c2 {
163                    pinmux = <RZV2M_PORT_PINMUX(3, 8, 2)>, /* SDA */
164                             <RZV2M_PORT_PINMUX(3, 9, 2)>; /* SCL */
165            };
166    };
167