1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller
8
9maintainers:
10  - Geert Uytterhoeven <geert+renesas@glider.be>
11  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
12
13description:
14  The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and
15  GPIO controller.
16  Pin multiplexing and GPIO configuration is performed on a per-pin basis.
17  Each port features up to 8 pins, each of them configurable for GPIO function
18  (port mode) or in alternate function mode.
19  Up to 8 different alternate function modes exist for each single pin.
20
21properties:
22  compatible:
23    oneOf:
24      - items:
25          - enum:
26              - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2}
27              - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
28
29      - items:
30          - enum:
31              - renesas,r9a07g054-pinctrl     # RZ/V2L
32          - const: renesas,r9a07g044-pinctrl  # RZ/G2{L,LC} fallback for RZ/V2L
33
34  reg:
35    maxItems: 1
36
37  gpio-controller: true
38
39  '#gpio-cells':
40    const: 2
41    description:
42      The first cell contains the global GPIO port index, constructed using the
43      RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
44      second cell represents consumer flag as mentioned in ../gpio/gpio.txt
45      E.g. "RZG2L_GPIO(39, 1)" for P39_1.
46
47  gpio-ranges:
48    maxItems: 1
49
50  clocks:
51    maxItems: 1
52
53  power-domains:
54    maxItems: 1
55
56  resets:
57    items:
58      - description: GPIO_RSTN signal
59      - description: GPIO_PORT_RESETN signal
60      - description: GPIO_SPARE_RESETN signal
61
62additionalProperties:
63  anyOf:
64    - type: object
65      allOf:
66        - $ref: pincfg-node.yaml#
67        - $ref: pinmux-node.yaml#
68
69      description:
70        Pin controller client devices use pin configuration subnodes (children
71        and grandchildren) for desired pin configuration.
72        Client device subnodes use below standard properties.
73
74      properties:
75        phandle: true
76        pinmux:
77          description:
78            Values are constructed from GPIO port number, pin number, and
79            alternate function configuration number using the RZG2L_PORT_PINMUX()
80            helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h>.
81        pins: true
82        drive-strength:
83          enum: [ 2, 4, 8, 12 ]
84        output-impedance-ohms:
85          enum: [ 33, 50, 66, 100 ]
86        power-source:
87          description: I/O voltage in millivolt.
88          enum: [ 1800, 2500, 3300 ]
89        slew-rate: true
90        gpio-hog: true
91        gpios: true
92        input-enable: true
93        output-high: true
94        output-low: true
95        line-name: true
96
97    - type: object
98      properties:
99        phandle: true
100
101      additionalProperties:
102        $ref: "#/additionalProperties/anyOf/0"
103
104allOf:
105  - $ref: "pinctrl.yaml#"
106
107required:
108  - compatible
109  - reg
110  - gpio-controller
111  - '#gpio-cells'
112  - gpio-ranges
113  - clocks
114  - power-domains
115  - resets
116
117examples:
118  - |
119    #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
120    #include <dt-bindings/clock/r9a07g044-cpg.h>
121
122    pinctrl: pinctrl@11030000 {
123            compatible = "renesas,r9a07g044-pinctrl";
124            reg = <0x11030000 0x10000>;
125
126            gpio-controller;
127            #gpio-cells = <2>;
128            gpio-ranges = <&pinctrl 0 0 392>;
129            clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
130            resets = <&cpg R9A07G044_GPIO_RSTN>,
131                     <&cpg R9A07G044_GPIO_PORT_RESETN>,
132                     <&cpg R9A07G044_GPIO_SPARE_RESETN>;
133            power-domains = <&cpg>;
134
135            scif0_pins: serial0 {
136                    pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* Tx */
137                             <RZG2L_PORT_PINMUX(38, 1, 1)>; /* Rx */
138            };
139
140            i2c1_pins: i2c1 {
141                    pins = "RIIC1_SDA", "RIIC1_SCL";
142                    input-enable;
143            };
144
145            sd1-pwr-en-hog {
146                    gpio-hog;
147                    gpios = <RZG2L_GPIO(39, 2) 0>;
148                    output-high;
149                    line-name = "sd1_pwr_en";
150            };
151
152            sdhi1_pins: sd1 {
153                    sd1_mux {
154                            pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */
155                                     <RZG2L_PORT_PINMUX(19, 1, 1)>; /* WP */
156                            power-source  = <3300>;
157                    };
158
159                    sd1_data {
160                            pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
161                            power-source  = <3300>;
162                    };
163
164                    sd1_ctrl {
165                            pins = "SD1_CLK", "SD1_CMD";
166                            power-source  = <3300>;
167                    };
168            };
169    };
170