1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SM8550 TLMM block
8
9maintainers:
10  - Abel Vesa <abel.vesa@linaro.org>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm SM8550 SoC.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sm8550-tlmm
21
22  reg:
23    maxItems: 1
24
25  interrupts: true
26  interrupt-controller: true
27  "#interrupt-cells": true
28  gpio-controller: true
29
30  gpio-reserved-ranges:
31    minItems: 1
32    maxItems: 105
33
34  gpio-line-names:
35    maxItems: 210
36
37  "#gpio-cells": true
38  gpio-ranges: true
39  wakeup-parent: true
40
41patternProperties:
42  "-state$":
43    oneOf:
44      - $ref: "#/$defs/qcom-sm8550-tlmm-state"
45      - patternProperties:
46          "-pins$":
47            $ref: "#/$defs/qcom-sm8550-tlmm-state"
48        additionalProperties: false
49
50$defs:
51  qcom-sm8550-tlmm-state:
52    type: object
53    description:
54      Pinctrl node's client devices use subnodes for desired pin configuration.
55      Client device subnodes use below standard properties.
56    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
57
58    properties:
59      pins:
60        description:
61          List of gpio pins affected by the properties specified in this
62          subnode.
63        items:
64          oneOf:
65            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
66            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
67        minItems: 1
68        maxItems: 36
69
70      function:
71        description:
72          Specify the alternative function to be configured for the specified
73          pins.
74        enum: [ aon_cci, aoss_cti, atest_char, atest_usb,
75                audio_ext_mclk0, audio_ext_mclk1, audio_ref_clk,
76                cam_aon_mclk4, cam_mclk, cci_async_in, cci_i2c_scl,
77                cci_i2c_sda, cci_timer, cmu_rng, coex_uart1_rx,
78                coex_uart1_tx, coex_uart2_rx, coex_uart2_tx,
79                cri_trng, dbg_out_clk, ddr_bist_complete,
80                ddr_bist_fail, ddr_bist_start, ddr_bist_stop,
81                ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot,
82                gcc_gp1, gcc_gp2, gcc_gp3, gpio, i2chub0_se0,
83                i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4,
84                i2chub0_se5, i2chub0_se6, i2chub0_se7, i2chub0_se8,
85                i2chub0_se9, i2s0_data0, i2s0_data1, i2s0_sck,
86                i2s0_ws, i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws,
87                ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0_out,
88                mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out,
89                mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2,
90                pcie0_clk_req_n, pcie1_clk_req_n, phase_flag,
91                pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1,
92                prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio,
93                qlink0_enable, qlink0_request, qlink0_wmss,
94                qlink1_enable, qlink1_request, qlink1_wmss,
95                qlink2_enable, qlink2_request, qlink2_wmss,
96                qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs,
97                qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4,
98                qup1_se5, qup1_se6, qup1_se7, qup2_se0,
99                qup2_se0_l0_mira, qup2_se0_l0_mirb, qup2_se0_l1_mira,
100                qup2_se0_l1_mirb, qup2_se0_l2_mira, qup2_se0_l2_mirb,
101                qup2_se0_l3_mira, qup2_se0_l3_mirb, qup2_se1,
102                qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6,
103                qup2_se7, sd_write_protect, sdc40, sdc41, sdc42,
104                sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2, tb_trig_sdc4,
105                tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout,
106                tgu_ch3_trigout, tmess_prng0, tmess_prng1, tmess_prng2,
107                tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3,
108                uim0_clk, uim0_data, uim0_present, uim0_reset,
109                uim1_clk, uim1_data, uim1_present, uim1_reset,
110                usb1_hs, usb_phy, vfr_0, vfr_1, vsense_trigger_mirnat ]
111
112      bias-disable: true
113      bias-pull-down: true
114      bias-pull-up: true
115      drive-strength: true
116      input-enable: true
117      output-high: true
118      output-low: true
119
120    required:
121      - pins
122
123    additionalProperties: false
124
125required:
126  - compatible
127  - reg
128
129additionalProperties: false
130
131examples:
132  - |
133    #include <dt-bindings/interrupt-controller/arm-gic.h>
134    tlmm: pinctrl@f100000 {
135        compatible = "qcom,sm8550-tlmm";
136        reg = <0x0f100000 0x300000>;
137        gpio-controller;
138        #gpio-cells = <2>;
139        gpio-ranges = <&tlmm 0 0 211>;
140        interrupt-controller;
141        #interrupt-cells = <2>;
142        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
143
144        gpio-wo-state {
145            pins = "gpio1";
146            function = "gpio";
147        };
148
149        uart-w-state {
150            rx-pins {
151                pins = "gpio26";
152                function = "qup2_se7";
153                bias-pull-up;
154            };
155
156            tx-pins {
157                pins = "gpio27";
158                function = "qup2_se7";
159                bias-disable;
160            };
161        };
162    };
163...
164