1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8450 SoC LPASS LPI TLMM
8
9maintainers:
10  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11
12description:
13  Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
14  (LPASS) Low Power Island (LPI) of Qualcomm SM8450 SoC.
15
16properties:
17  compatible:
18    const: qcom,sm8450-lpass-lpi-pinctrl
19
20  reg:
21    items:
22      - description: LPASS LPI TLMM Control and Status registers
23      - description: LPASS LPI pins SLEW registers
24
25  clocks:
26    items:
27      - description: LPASS Core voting clock
28      - description: LPASS Audio voting clock
29
30  clock-names:
31    items:
32      - const: core
33      - const: audio
34
35  gpio-controller: true
36
37  "#gpio-cells":
38    description: Specifying the pin number and flags, as defined in
39      include/dt-bindings/gpio/gpio.h
40    const: 2
41
42  gpio-ranges:
43    maxItems: 1
44
45patternProperties:
46  "-state$":
47    oneOf:
48      - $ref: "#/$defs/qcom-sm8450-lpass-state"
49      - patternProperties:
50          "-pins$":
51            $ref: "#/$defs/qcom-sm8450-lpass-state"
52        additionalProperties: false
53
54$defs:
55  qcom-sm8450-lpass-state:
56    type: object
57    description:
58      Pinctrl node's client devices use subnodes for desired pin configuration.
59      Client device subnodes use below standard properties.
60    $ref: /schemas/pinctrl/pincfg-node.yaml
61
62    properties:
63      pins:
64        description:
65          List of gpio pins affected by the properties specified in this
66          subnode.
67        items:
68          pattern: "^gpio([0-9]|[1-2][0-9])$"
69
70      function:
71        enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
72                dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic4_clk,
73                dmic4_data, i2s2_clk, i2s2_ws, dmic3_clk, dmic3_data,
74                qua_mi2s_sclk, qua_mi2s_ws, qua_mi2s_data, i2s1_clk, i2s1_ws,
75                i2s1_data, wsa_swr_clk, wsa_swr_data, wsa2_swr_clk,
76                wsa2_swr_data, i2s2_data, i2s4_ws, i2s4_clk, i2s4_data,
77                slimbus_clk, i2s3_clk, i2s3_ws, i2s3_data, slimbus_data,
78                ext_mclk1_c, ext_mclk1_b, ext_mclk1_a, ext_mclk1_d,
79                ext_mclk1_e ]
80        description:
81          Specify the alternative function to be configured for the specified
82          pins.
83
84      drive-strength:
85        enum: [2, 4, 6, 8, 10, 12, 14, 16]
86        default: 2
87        description:
88          Selects the drive strength for the specified pins, in mA.
89
90      slew-rate:
91        enum: [0, 1, 2, 3]
92        default: 0
93        description: |
94          0: No adjustments
95          1: Higher Slew rate (faster edges)
96          2: Lower Slew rate (slower edges)
97          3: Reserved (No adjustments)
98
99      bias-pull-down: true
100
101      bias-pull-up: true
102
103      bias-disable: true
104
105      output-high: true
106
107      output-low: true
108
109    required:
110      - pins
111      - function
112
113    additionalProperties: false
114
115allOf:
116  - $ref: pinctrl.yaml#
117
118required:
119  - compatible
120  - reg
121  - clocks
122  - clock-names
123  - gpio-controller
124  - "#gpio-cells"
125  - gpio-ranges
126
127additionalProperties: false
128
129examples:
130  - |
131    #include <dt-bindings/sound/qcom,q6afe.h>
132    pinctrl@3440000 {
133        compatible = "qcom,sm8450-lpass-lpi-pinctrl";
134        reg = <0x3440000 0x20000>,
135              <0x34d0000 0x10000>;
136        clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
137                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
138        clock-names = "core", "audio";
139        gpio-controller;
140        #gpio-cells = <2>;
141        gpio-ranges = <&lpi_tlmm 0 0 23>;
142
143        wsa-swr-active-state {
144            clk-pins {
145                pins = "gpio10";
146                function = "wsa_swr_clk";
147                drive-strength = <2>;
148                slew-rate = <1>;
149                bias-disable;
150            };
151
152            data-pins {
153                pins = "gpio11";
154                function = "wsa_swr_data";
155                drive-strength = <2>;
156                slew-rate = <1>;
157            };
158        };
159
160        tx-swr-sleep-clk-state {
161            pins = "gpio0";
162            function = "swr_tx_clk";
163            drive-strength = <2>;
164            bias-pull-down;
165        };
166    };
167