1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SM8250 TLMM block
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12description:
13  Top Level Mode Multiplexer pin controller in the Qualcomm SM8250 SoC.
14
15properties:
16  compatible:
17    const: qcom,sm8250-pinctrl
18
19  reg:
20    maxItems: 3
21
22  reg-names:
23    items:
24      - const: west
25      - const: south
26      - const: north
27
28  interrupts: true
29  interrupt-controller: true
30  "#interrupt-cells": true
31  gpio-controller: true
32  "#gpio-cells": true
33  gpio-ranges: true
34  wakeup-parent: true
35
36  gpio-reserved-ranges:
37    minItems: 1
38    maxItems: 90
39
40  gpio-line-names:
41    maxItems: 180
42
43patternProperties:
44  "-state$":
45    oneOf:
46      - $ref: "#/$defs/qcom-sm8250-tlmm-state"
47      - patternProperties:
48          "-pins$":
49            $ref: "#/$defs/qcom-sm8250-tlmm-state"
50        additionalProperties: false
51
52$defs:
53  qcom-sm8250-tlmm-state:
54    type: object
55    description:
56      Pinctrl node's client devices use subnodes for desired pin configuration.
57      Client device subnodes use below standard properties.
58    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
59
60    properties:
61      pins:
62        description:
63          List of gpio pins affected by the properties specified in this
64          subnode.
65        items:
66          oneOf:
67            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
68            - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
69        minItems: 1
70        maxItems: 36
71
72      function:
73        description:
74          Specify the alternative function to be configured for the specified
75          pins.
76
77        enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c,
78                cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
79                cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
80                ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
81                ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
82                mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
83                mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
84                mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci_e1,
85                pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset,
86                pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qspi2, qspi3,
87                qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14,
88                qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5, qup6,
89                qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41,
90                sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch0, tgu_ch1,
91                tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsif0_data,
92                tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, tsif1_en,
93                tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigger ]
94
95      bias-pull-down: true
96      bias-pull-up: true
97      bias-disable: true
98      drive-strength: true
99      input-enable: true
100      output-high: true
101      output-low: true
102
103    required:
104      - pins
105
106    additionalProperties: false
107
108allOf:
109  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
110
111required:
112  - compatible
113  - reg
114  - reg-names
115
116additionalProperties: false
117
118examples:
119  - |
120    #include <dt-bindings/interrupt-controller/arm-gic.h>
121    pinctrl@1f00000 {
122        compatible = "qcom,sm8250-pinctrl";
123        reg = <0x0f100000 0x300000>,
124              <0x0f500000 0x300000>,
125              <0x0f900000 0x300000>;
126        reg-names = "west", "south", "north";
127        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
128        gpio-controller;
129        #gpio-cells = <2>;
130        interrupt-controller;
131        #interrupt-cells = <2>;
132        gpio-ranges = <&tlmm 0 0 180>;
133        wakeup-parent = <&pdc>;
134    };
135