1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8150-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8150 TLMM pin controller
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
13description:
14  Top Level Mode Multiplexer pin controller in Qualcomm SM8150 SoC.
15
16properties:
17  compatible:
18    const: qcom,sm8150-pinctrl
19
20  reg:
21    maxItems: 4
22
23  reg-names:
24    items:
25      - const: west
26      - const: east
27      - const: north
28      - const: south
29
30  interrupts: true
31  interrupt-controller: true
32  "#interrupt-cells": true
33  gpio-controller: true
34  "#gpio-cells": true
35  gpio-ranges: true
36  wakeup-parent: true
37
38  gpio-reserved-ranges:
39    minItems: 1
40    maxItems: 88
41
42  gpio-line-names:
43    maxItems: 175
44
45patternProperties:
46  "-state$":
47    oneOf:
48      - $ref: "#/$defs/qcom-sm8150-tlmm-state"
49      - patternProperties:
50          "-pins$":
51            $ref: "#/$defs/qcom-sm8150-tlmm-state"
52        additionalProperties: false
53
54$defs:
55  qcom-sm8150-tlmm-state:
56    type: object
57    description:
58      Pinctrl node's client devices use subnodes for desired pin configuration.
59      Client device subnodes use below standard properties.
60    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
61
62    properties:
63      pins:
64        description:
65          List of gpio pins affected by the properties specified in this
66          subnode.
67        items:
68          oneOf:
69            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
70            - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
71        minItems: 1
72        maxItems: 36
73
74      function:
75        description:
76          Specify the alternative function to be configured for the specified
77          pins.
78
79        enum: [ adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char,
80                atest_char0, atest_char1, atest_char2, atest_char3, audio_ref,
81                atest_usb1, atest_usb2, atest_usb10, atest_usb11, atest_usb12,
82                atest_usb13, atest_usb20, atest_usb21, atest_usb22, atest_usb2,
83                atest_usb23, btfm_slimbus, cam_mclk, cci_async, cci_i2c,
84                cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
85                cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
86                ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd, emac_phy, emac_pps,
87                gcc_gp1, gcc_gp2, gcc_gp3, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s,
88                jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1,
89                mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator,
90                pci_e0, phase_flag, pll_bypassnl, pll_bist, pci_e1, pll_reset,
91                pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti,
92                qlink_request, qlink_enable, qspi0, qspi1, qspi2, qspi3,
93                qspi_clk, qspi_cs, qua_mi2s, qup0, qup1, qup2, qup3, qup4,
94                qup5, qup6, qup7, qup8, qup9, qup10, qup11, qup12, qup13,
95                qup14, qup15, qup16, qup17, qup18, qup19, qup_l4, qup_l5,
96                qup_l6, rgmii, sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu,
97                ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
98                tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt, usb2phy_ac,
99                usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,
100                wlan2_adc0, wlan2_adc1, wmss_reset ]
101
102      bias-pull-down: true
103      bias-pull-up: true
104      bias-disable: true
105      drive-strength: true
106      input-enable: true
107      output-high: true
108      output-low: true
109
110    required:
111      - pins
112
113    additionalProperties: false
114
115allOf:
116  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
117
118required:
119  - compatible
120  - reg
121  - reg-names
122
123additionalProperties: false
124
125examples:
126  - |
127    #include <dt-bindings/interrupt-controller/arm-gic.h>
128
129    tlmm: pinctrl@3100000 {
130        compatible = "qcom,sm8150-pinctrl";
131        reg = <0x03100000 0x300000>,
132              <0x03500000 0x300000>,
133              <0x03900000 0x300000>,
134              <0x03d00000 0x300000>;
135        reg-names = "west", "east", "north", "south";
136        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
137        gpio-ranges = <&tlmm 0 0 176>;
138        gpio-controller;
139        #gpio-cells = <2>;
140        interrupt-controller;
141        #interrupt-cells = <2>;
142        wakeup-parent = <&pdc>;
143
144        qup-spi0-default-state {
145            pins = "gpio0", "gpio1", "gpio2", "gpio3";
146            function = "qup0";
147            drive-strength = <6>;
148            bias-disable;
149        };
150
151        pcie1-default-state {
152            perst-pins {
153                pins = "gpio102";
154                function = "gpio";
155                drive-strength = <2>;
156                bias-pull-down;
157            };
158
159            clkreq-pins {
160                pins = "gpio103";
161                function = "pci_e1";
162                drive-strength = <2>;
163                bias-pull-up;
164            };
165
166            wake-pins {
167                pins = "gpio104";
168                function = "gpio";
169                drive-strength = <2>;
170                bias-pull-up;
171            };
172        };
173    };
174