1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8150-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8150 TLMM pin controller
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
13description:
14  Top Level Mode Multiplexer pin controller in Qualcomm SM8150 SoC.
15
16properties:
17  compatible:
18    const: qcom,sm8150-pinctrl
19
20  reg:
21    maxItems: 4
22
23  reg-names:
24    items:
25      - const: west
26      - const: east
27      - const: north
28      - const: south
29
30  interrupts:
31    maxItems: 1
32
33  interrupt-controller: true
34  "#interrupt-cells": true
35  gpio-controller: true
36  "#gpio-cells": true
37  gpio-ranges: true
38  wakeup-parent: true
39
40  gpio-reserved-ranges:
41    minItems: 1
42    maxItems: 88
43
44  gpio-line-names:
45    maxItems: 175
46
47patternProperties:
48  "-state$":
49    oneOf:
50      - $ref: "#/$defs/qcom-sm8150-tlmm-state"
51      - patternProperties:
52          "-pins$":
53            $ref: "#/$defs/qcom-sm8150-tlmm-state"
54        additionalProperties: false
55
56$defs:
57  qcom-sm8150-tlmm-state:
58    type: object
59    description:
60      Pinctrl node's client devices use subnodes for desired pin configuration.
61      Client device subnodes use below standard properties.
62    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
63
64    properties:
65      pins:
66        description:
67          List of gpio pins affected by the properties specified in this
68          subnode.
69        items:
70          oneOf:
71            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
72            - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
73        minItems: 1
74        maxItems: 36
75
76      function:
77        description:
78          Specify the alternative function to be configured for the specified
79          pins.
80
81        enum: [ adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char,
82                atest_char0, atest_char1, atest_char2, atest_char3, audio_ref,
83                atest_usb1, atest_usb2, atest_usb10, atest_usb11, atest_usb12,
84                atest_usb13, atest_usb20, atest_usb21, atest_usb22, atest_usb2,
85                atest_usb23, btfm_slimbus, cam_mclk, cci_async, cci_i2c,
86                cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
87                cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
88                ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd, emac_phy, emac_pps,
89                gcc_gp1, gcc_gp2, gcc_gp3, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s,
90                jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1,
91                mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator,
92                pci_e0, phase_flag, pll_bypassnl, pll_bist, pci_e1, pll_reset,
93                pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti,
94                qlink_request, qlink_enable, qspi0, qspi1, qspi2, qspi3,
95                qspi_clk, qspi_cs, qua_mi2s, qup0, qup1, qup2, qup3, qup4,
96                qup5, qup6, qup7, qup8, qup9, qup10, qup11, qup12, qup13,
97                qup14, qup15, qup16, qup17, qup18, qup19, qup_l4, qup_l5,
98                qup_l6, rgmii, sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu,
99                ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
100                tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt, usb2phy_ac,
101                usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,
102                wlan2_adc0, wlan2_adc1, wmss_reset ]
103
104      bias-pull-down: true
105      bias-pull-up: true
106      bias-disable: true
107      drive-strength: true
108      input-enable: true
109      output-high: true
110      output-low: true
111
112    required:
113      - pins
114
115    additionalProperties: false
116
117allOf:
118  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
119
120required:
121  - compatible
122  - reg
123  - reg-names
124
125additionalProperties: false
126
127examples:
128  - |
129    #include <dt-bindings/interrupt-controller/arm-gic.h>
130
131    tlmm: pinctrl@3100000 {
132        compatible = "qcom,sm8150-pinctrl";
133        reg = <0x03100000 0x300000>,
134              <0x03500000 0x300000>,
135              <0x03900000 0x300000>,
136              <0x03d00000 0x300000>;
137        reg-names = "west", "east", "north", "south";
138        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
139        gpio-ranges = <&tlmm 0 0 176>;
140        gpio-controller;
141        #gpio-cells = <2>;
142        interrupt-controller;
143        #interrupt-cells = <2>;
144        wakeup-parent = <&pdc>;
145
146        qup-spi0-default-state {
147            pins = "gpio0", "gpio1", "gpio2", "gpio3";
148            function = "qup0";
149            drive-strength = <6>;
150            bias-disable;
151        };
152
153        pcie1-default-state {
154            perst-pins {
155                pins = "gpio102";
156                function = "gpio";
157                drive-strength = <2>;
158                bias-pull-down;
159            };
160
161            clkreq-pins {
162                pins = "gpio103";
163                function = "pci_e1";
164                drive-strength = <2>;
165                bias-pull-up;
166            };
167
168            wake-pins {
169                pins = "gpio104";
170                function = "gpio";
171                drive-strength = <2>;
172                bias-pull-up;
173            };
174        };
175    };
176