1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm6125-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6title: Qualcomm Technologies, Inc. SM6125 TLMM block
7
8maintainers:
9  - Martin Botka <martin.botka@somainline.org>
10
11description:
12  Top Level Mode Multiplexer pin controller in Qualcomm SM6125 SoC.
13
14allOf:
15  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
16
17properties:
18  compatible:
19    const: qcom,sm6125-tlmm
20
21  reg:
22    maxItems: 3
23
24  reg-names:
25    items:
26      - const: west
27      - const: south
28      - const: east
29
30  interrupts: true
31  interrupt-controller: true
32  "#interrupt-cells": true
33  gpio-controller: true
34  gpio-reserved-ranges: true
35  "#gpio-cells": true
36  gpio-ranges: true
37  wakeup-parent: true
38
39required:
40  - compatible
41  - reg
42  - reg-names
43
44additionalProperties: false
45
46patternProperties:
47  "-state$":
48    oneOf:
49      - $ref: "#/$defs/qcom-sm6125-tlmm-state"
50      - patternProperties:
51          "-pins$":
52            $ref: "#/$defs/qcom-sm6125-tlmm-state"
53        additionalProperties: false
54
55$defs:
56  qcom-sm6125-tlmm-state:
57    type: object
58    description:
59      Pinctrl node's client devices use subnodes for desired pin configuration.
60      Client device subnodes use below standard properties.
61    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
62
63    properties:
64      pins:
65        description:
66          List of gpio pins affected by the properties specified in this
67          subnode.
68        items:
69          oneOf:
70            - pattern: "^gpio[0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2]$"
71            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
72        minItems: 1
73        maxItems: 36
74
75      function:
76        description:
77          Specify the alternative function to be configured for the specified
78          pins.
79
80        enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
81                atest_char2, atest_char3, atest_tsens, atest_tsens2, atest_usb1,
82                atest_usb10, atest_usb11, atest_usb12, atest_usb13, atest_usb2,
83                atest_usb20, atest_usb21, atest_usb22, atest_usb23, aud_sb,
84                audio_ref, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
85                cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, cri_trng,
86                cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
87                ddr_pxi2, ddr_pxi3, debug_hot, dmic0_clk, dmic0_data, dmic1_clk,
88                dmic1_data, dp_hot, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
89                gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en,
90                ldo_update, m_voc, mclk1, mclk2, mdp_vsync, mdp_vsync0, mdp_vsync1,
91                mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5, mpm_pwr, mss_lte,
92                nav_pps, pa_indicator, phase_flag, pll_bist, pll_bypassnl, pll_reset,
93                pri_mi2s, pri_mi2s_ws, prng_rosc, qca_sb, qdss_cti, qdss, qlink_enable,
94                qlink_request, qua_mi2s, qui_mi2s, qup00, qup01, qup02, qup03, qup04,
95                qup10, qup11, qup12, qup13, qup14, sd_write, sec_mi2s, sp_cmu, swr_rx,
96                swr_tx, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm,
97                uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
98                uim2_present, uim2_reset, unused1, unused2, usb_phy, vfr_1, vsense_trigger,
99                wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data ]
100
101
102      bias-disable: true
103      bias-pull-down: true
104      bias-pull-up: true
105      drive-strength: true
106      input-enable: true
107      output-high: true
108      output-low: true
109
110    required:
111      - pins
112
113    additionalProperties: false
114
115examples:
116  - |
117    #include <dt-bindings/interrupt-controller/arm-gic.h>
118    pinctrl@500000 {
119        compatible = "qcom,sm6125-tlmm";
120        reg = <0x00500000 0x400000>,
121              <0x00900000 0x400000>,
122              <0x00d00000 0x400000>;
123        reg-names = "west", "south", "east";
124        interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
125        gpio-controller;
126        gpio-ranges = <&tlmm 0 0 134>;
127        #gpio-cells = <2>;
128        interrupt-controller;
129        #interrupt-cells = <2>;
130
131        sdc2-off-state {
132            clk-pins {
133                pins = "sdc2_clk";
134                drive-strength = <2>;
135                bias-disable;
136            };
137
138            cmd-pins {
139                pins = "sdc2_cmd";
140                drive-strength = <2>;
141                bias-pull-up;
142            };
143
144            data-pins {
145                pins = "sdc2_data";
146                drive-strength = <2>;
147                bias-pull-up;
148            };
149        };
150    };
151