1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sdx55-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SDX55 TLMM block
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm SDX55 SoC.
14
15properties:
16  compatible:
17    const: qcom,sdx55-pinctrl
18
19  reg:
20    description: Specifies the base address and size of the TLMM register space
21    maxItems: 1
22
23  interrupts: true
24  interrupt-controller: true
25  "#interrupt-cells": true
26  gpio-controller: true
27  "#gpio-cells": true
28  gpio-ranges: true
29
30  gpio-reserved-ranges:
31    maxItems: 1
32
33patternProperties:
34  "-state$":
35    oneOf:
36      - $ref: "#/$defs/qcom-sdx55-tlmm-state"
37      - patternProperties:
38          "-pins$":
39            $ref: "#/$defs/qcom-sdx55-tlmm-state"
40        additionalProperties: false
41
42$defs:
43  qcom-sdx55-tlmm-state:
44    type: object
45    description:
46      Pinctrl node's client devices use subnodes for desired pin configuration.
47      Client device subnodes use below standard properties.
48    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
49
50    properties:
51      pins:
52        description:
53          List of gpio pins affected by the properties specified in this subnode.
54        items:
55          oneOf:
56            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$"
57            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
58        minItems: 1
59        maxItems: 36
60
61      function:
62        description:
63          Specify the alternative function to be configured for the specified
64          pins. Functions are only valid for gpio pins.
65        enum: [ adsp_ext, atest, audio_ref, bimc_dte0, bimc_dte1, blsp_i2c1,
66                blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_spi1, blsp_spi2,
67                blsp_spi3, blsp_spi4, blsp_uart1, blsp_uart2, blsp_uart3,
68                blsp_uart4, char_exec, coex_uart, coex_uart2, cri_trng,
69                cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
70                ebi0_wrcdc, ebi2_a, ebi2_lcd, emac_gcc0, emac_gcc1,
71                emac_pps0, emac_pps1, ext_dbg, gcc_gp1, gcc_gp2, gcc_gp3,
72                gcc_plltest, gpio, i2s_mclk, jitter_bist, ldo_en, ldo_update,
73                mgpi_clk, m_voc, native_char, native_char0, native_char1,
74                native_char2, native_char3, native_tsens, native_tsense,
75                nav_gpio, pa_indicator, pcie_clkreq, pci_e, pll_bist, pll_ref,
76                pll_test, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio,
77                qdss_gpio0, qdss_gpio1, qdss_gpio2, qdss_gpio3, qdss_gpio4,
78                qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9,
79                qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13,
80                qdss_gpio14, qdss_gpio15, qdss_stm0, qdss_stm1, qdss_stm2,
81                qdss_stm3, qdss_stm4, qdss_stm5, qdss_stm6, qdss_stm7,
82                qdss_stm8, qdss_stm9, qdss_stm10, qdss_stm11, qdss_stm12,
83                qdss_stm13, qdss_stm14, qdss_stm15, qdss_stm16, qdss_stm17,
84                qdss_stm18, qdss_stm19, qdss_stm20, qdss_stm21, qdss_stm22,
85                qdss_stm23, qdss_stm24, qdss_stm25, qdss_stm26, qdss_stm27,
86                qdss_stm28, qdss_stm29, qdss_stm30, qdss_stm31, qlink0_en,
87                qlink0_req, qlink0_wmss, qlink1_en, qlink1_req, qlink1_wmss,
88                spmi_coex, sec_mi2s, spmi_vgi, tgu_ch0, uim1_clk, uim1_data,
89                uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present,
90                uim2_reset, usb2phy_ac, vsense_trigger ]
91
92      bias-pull-down: true
93      bias-pull-up: true
94      bias-disable: true
95      drive-strength: true
96      output-high: true
97      output-low: true
98
99    required:
100      - pins
101
102    additionalProperties: false
103
104allOf:
105  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
106
107required:
108  - compatible
109  - reg
110
111additionalProperties: false
112
113examples:
114  - |
115    #include <dt-bindings/interrupt-controller/arm-gic.h>
116    tlmm: pinctrl@1f00000 {
117        compatible = "qcom,sdx55-pinctrl";
118        reg = <0x0f100000 0x300000>;
119        gpio-controller;
120        #gpio-cells = <2>;
121        gpio-ranges = <&tlmm 0 0 108>;
122        interrupt-controller;
123        #interrupt-cells = <2>;
124        interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
125
126        serial-state {
127            pins = "gpio8", "gpio9";
128            function = "blsp_uart3";
129            drive-strength = <8>;
130            bias-disable;
131        };
132    };
133
134...
135