1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sdx55-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SDX55 TLMM block
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description: |
13  This binding describes the Top Level Mode Multiplexer block found in the
14  SDX55 platform.
15
16properties:
17  compatible:
18    const: qcom,sdx55-pinctrl
19
20  reg:
21    description: Specifies the base address and size of the TLMM register space
22    maxItems: 1
23
24  interrupts:
25    description: Specifies the TLMM summary IRQ
26    maxItems: 1
27
28  interrupt-controller: true
29
30  '#interrupt-cells':
31    description: Specifies the PIN numbers and Flags, as defined in
32      include/dt-bindings/interrupt-controller/irq.h
33    const: 2
34
35  gpio-controller: true
36
37  '#gpio-cells':
38    description: Specifying the pin number and flags, as defined in
39      include/dt-bindings/gpio/gpio.h
40    const: 2
41
42  gpio-ranges:
43    maxItems: 1
44
45  gpio-reserved-ranges:
46    maxItems: 1
47
48#PIN CONFIGURATION NODES
49patternProperties:
50  '-pins$':
51    type: object
52    description:
53      Pinctrl node's client devices use subnodes for desired pin configuration.
54      Client device subnodes use below standard properties.
55    $ref: "/schemas/pinctrl/pincfg-node.yaml"
56
57    properties:
58      pins:
59        description:
60          List of gpio pins affected by the properties specified in this subnode.
61        items:
62          oneOf:
63            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$"
64            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
65        minItems: 1
66        maxItems: 36
67
68      function:
69        description:
70          Specify the alternative function to be configured for the specified
71          pins. Functions are only valid for gpio pins.
72        enum: [ adsp_ext, atest, audio_ref, bimc_dte0, bimc_dte1, blsp_i2c1,
73                blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_spi1, blsp_spi2,
74                blsp_spi3, blsp_spi4, blsp_uart1, blsp_uart2, blsp_uart3,
75                blsp_uart4, char_exec, coex_uart, coex_uart2, cri_trng,
76                cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
77                ebi0_wrcdc, ebi2_a, ebi2_lcd, emac_gcc0, emac_gcc1,
78                emac_pps0, emac_pps1, ext_dbg, gcc_gp1, gcc_gp2, gcc_gp3,
79                gcc_plltest, gpio, i2s_mclk, jitter_bist, ldo_en, ldo_update,
80                mgpi_clk, m_voc, native_char, native_char0, native_char1,
81                native_char2, native_char3, native_tsens, native_tsense,
82                nav_gpio, pa_indicator, pcie_clkreq, pci_e, pll_bist, pll_ref,
83                pll_test, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio,
84                qdss_gpio0, qdss_gpio1, qdss_gpio2, qdss_gpio3, qdss_gpio4,
85                qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9,
86                qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13,
87                qdss_gpio14, qdss_gpio15, qdss_stm0, qdss_stm1, qdss_stm2,
88                qdss_stm3, qdss_stm4, qdss_stm5, qdss_stm6, qdss_stm7,
89                qdss_stm8, qdss_stm9, qdss_stm10, qdss_stm11, qdss_stm12,
90                qdss_stm13, qdss_stm14, qdss_stm15, qdss_stm16, qdss_stm17,
91                qdss_stm18, qdss_stm19, qdss_stm20, qdss_stm21, qdss_stm22,
92                qdss_stm23, qdss_stm24, qdss_stm25, qdss_stm26, qdss_stm27,
93                qdss_stm28, qdss_stm29, qdss_stm30, qdss_stm31, qlink0_en,
94                qlink0_req, qlink0_wmss, qlink1_en, qlink1_req, qlink1_wmss,
95                spmi_coex, sec_mi2s, spmi_vgi, tgu_ch0, uim1_clk, uim1_data,
96                uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present,
97                uim2_reset, usb2phy_ac, vsense_trigger ]
98
99      drive-strength:
100        enum: [2, 4, 6, 8, 10, 12, 14, 16]
101        default: 2
102        description:
103          Selects the drive strength for the specified pins, in mA.
104
105      bias-pull-down: true
106
107      bias-pull-up: true
108
109      bias-disable: true
110
111      output-high: true
112
113      output-low: true
114
115    required:
116      - pins
117      - function
118
119    additionalProperties: false
120
121required:
122  - compatible
123  - reg
124  - interrupts
125  - interrupt-controller
126  - '#interrupt-cells'
127  - gpio-controller
128  - '#gpio-cells'
129  - gpio-ranges
130
131additionalProperties: false
132
133examples:
134  - |
135        #include <dt-bindings/interrupt-controller/arm-gic.h>
136        tlmm: pinctrl@1f00000 {
137                compatible = "qcom,sdx55-pinctrl";
138                reg = <0x0f100000 0x300000>;
139                gpio-controller;
140                #gpio-cells = <2>;
141                gpio-ranges = <&tlmm 0 0 108>;
142                interrupt-controller;
143                #interrupt-cells = <2>;
144                interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
145
146                serial-pins {
147                        pins = "gpio8", "gpio9";
148                        function = "blsp_uart3";
149                        drive-strength = <8>;
150                        bias-disable;
151                };
152        };
153
154...
155