1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sdm670-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SDM670 TLMM block
8
9maintainers:
10  - Richard Acayan <mailingradian@gmail.com>
11
12description: |
13  The Top Level Mode Multiplexer (TLMM) block found in the SDM670 platform.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sdm670-tlmm
21
22  reg:
23    maxItems: 1
24
25  interrupts: true
26  interrupt-controller: true
27  "#interrupt-cells": true
28  gpio-controller: true
29  gpio-reserved-ranges:
30    minItems: 1
31    maxItems: 75
32
33  "#gpio-cells": true
34  gpio-ranges: true
35  wakeup-parent: true
36
37required:
38  - compatible
39  - reg
40
41additionalProperties: false
42
43patternProperties:
44  "-state$":
45    oneOf:
46      - $ref: "#/$defs/qcom-sdm670-tlmm-state"
47      - patternProperties:
48          "-pins$":
49            $ref: "#/$defs/qcom-sdm670-tlmm-state"
50        additionalProperties: false
51
52$defs:
53  qcom-sdm670-tlmm-state:
54    type: object
55    description:
56      Pinctrl node's client devices use subnodes for desired pin configuration.
57      Client device subnodes use below standard properties.
58    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
59
60    properties:
61      pins:
62        description:
63          List of gpio pins affected by the properties specified in this
64          subnode.
65        items:
66          oneOf:
67            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
68            - enum: [ ufs_reset, sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
69                      sdc2_clk, sdc2_cmd, sdc2_data ]
70        minItems: 1
71        maxItems: 36
72
73      function:
74        description:
75          Specify the alternative function to be configured for the specified
76          pins.
77
78        enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2, atest_usb1, atest_usb10,
79                atest_usb11, atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21,
80                atest_usb22, atest_usb23, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
81                cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, dbg_out, ddr_bist,
82                ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
83                gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en, ldo_update,
84                lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3,
85                mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl,
86                pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss, qlink_enable,
87                qlink_request, qua_mi2s, qup0, qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2,
88                qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sdc4_clk,
89                sdc4_cmd, sdc4_data, sd_write, sec_mi2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2,
90                tgu_ch3, tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync, tsif2_clk,
91                tsif2_data, tsif2_en, tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
92                uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, vfr_1,
93                vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data, ]
94
95
96      bias-disable: true
97      bias-pull-down: true
98      bias-pull-up: true
99      drive-strength: true
100      input-enable: true
101      output-high: true
102      output-low: true
103
104    required:
105      - pins
106
107    additionalProperties: false
108
109examples:
110  - |
111    #include <dt-bindings/interrupt-controller/arm-gic.h>
112    pinctrl@3400000 {
113        compatible = "qcom,sdm670-tlmm";
114        reg = <0x03400000 0x300000>;
115        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
116        gpio-controller;
117        #gpio-cells = <2>;
118        interrupt-controller;
119        #interrupt-cells = <2>;
120        gpio-ranges = <&tlmm 0 0 151>;
121
122        qup-i2c9-state {
123            pins = "gpio6", "gpio7";
124            function = "qup9";
125        };
126    };
127...
128