1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
8  Low Power Island (LPI) TLMM block
9
10maintainers:
11  - Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
12  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13
14description: |
15  This binding describes the Top Level Mode Multiplexer block found in the
16  LPASS LPI IP on most Qualcomm SoCs
17
18properties:
19  compatible:
20    const: qcom,sc7280-lpass-lpi-pinctrl
21
22  qcom,adsp-bypass-mode:
23    description:
24      Tells ADSP is in bypass mode.
25    type: boolean
26
27  reg:
28    minItems: 2
29    maxItems: 2
30
31  gpio-controller: true
32
33  '#gpio-cells':
34    description: Specifying the pin number and flags, as defined in
35      include/dt-bindings/gpio/gpio.h
36    const: 2
37
38  gpio-ranges:
39    maxItems: 1
40
41#PIN CONFIGURATION NODES
42patternProperties:
43  '-pins$':
44    type: object
45    description:
46      Pinctrl node's client devices use subnodes for desired pin configuration.
47      Client device subnodes use below standard properties.
48    $ref: "/schemas/pinctrl/pincfg-node.yaml"
49
50    properties:
51      pins:
52        description:
53          List of gpio pins affected by the properties specified in this
54          subnode.
55        items:
56          oneOf:
57            - pattern: "^gpio([0-9]|[1-9][0-9])$"
58        minItems: 1
59        maxItems: 15
60
61      function:
62        enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
63                qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
64                dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
65                i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
66                dmic3_data, i2s2_data ]
67        description:
68          Specify the alternative function to be configured for the specified
69          pins.
70
71      drive-strength:
72        enum: [2, 4, 6, 8, 10, 12, 14, 16]
73        default: 2
74        description:
75          Selects the drive strength for the specified pins, in mA.
76
77      slew-rate:
78        enum: [0, 1, 2, 3]
79        default: 0
80        description: |
81            0: No adjustments
82            1: Higher Slew rate (faster edges)
83            2: Lower Slew rate (slower edges)
84            3: Reserved (No adjustments)
85
86      bias-pull-down: true
87
88      bias-pull-up: true
89
90      bias-disable: true
91
92      output-high: true
93
94      output-low: true
95
96    required:
97      - pins
98      - function
99
100    additionalProperties: false
101
102required:
103  - compatible
104  - reg
105  - gpio-controller
106  - '#gpio-cells'
107  - gpio-ranges
108
109additionalProperties: false
110
111examples:
112  - |
113    lpass_tlmm: pinctrl@33c0000 {
114        compatible = "qcom,sc7280-lpass-lpi-pinctrl";
115        reg = <0x33c0000 0x20000>,
116              <0x3550000 0x10000>;
117        gpio-controller;
118        #gpio-cells = <2>;
119        gpio-ranges = <&lpass_tlmm 0 0 15>;
120    };
121