1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,msm8994-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm MSM8994 TLMM pin controller
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
13description:
14  Top Level Mode Multiplexer pin controller in Qualcomm MSM8994 SoC.
15
16properties:
17  compatible:
18    enum:
19      - qcom,msm8992-pinctrl
20      - qcom,msm8994-pinctrl
21
22  reg:
23    maxItems: 1
24
25  interrupts: true
26  interrupt-controller: true
27  "#interrupt-cells": true
28  gpio-controller: true
29  "#gpio-cells": true
30  gpio-ranges: true
31  wakeup-parent: true
32
33  gpio-reserved-ranges:
34    minItems: 1
35    maxItems: 75
36
37  gpio-line-names:
38    maxItems: 150
39
40patternProperties:
41  "-state$":
42    oneOf:
43      - $ref: "#/$defs/qcom-msm8994-tlmm-state"
44      - patternProperties:
45          "-pins$":
46            $ref: "#/$defs/qcom-msm8994-tlmm-state"
47        additionalProperties: false
48
49$defs:
50  qcom-msm8994-tlmm-state:
51    type: object
52    description:
53      Pinctrl node's client devices use subnodes for desired pin configuration.
54      Client device subnodes use below standard properties.
55    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
56
57    properties:
58      pins:
59        description:
60          List of gpio pins affected by the properties specified in this
61          subnode.
62        items:
63          oneOf:
64            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
65            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
66                      sdc2_cmd, sdc2_data, sdc3_clk, sdc3_cmd, sdc3_data ]
67        minItems: 1
68        maxItems: 36
69
70      function:
71        description:
72          Specify the alternative function to be configured for the specified
73          pins.
74
75        enum: [ gpio, audio_ref_clk, blsp_i2c1, blsp_i2c2, blsp_i2c3,
76                blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
77                blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, blsp_spi1,
78                blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3, blsp_spi2,
79                blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3,
80                blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8,
81                blsp_spi9, blsp_spi10, blsp_spi10_cs1, blsp_spi10_cs2,
82                blsp_spi10_cs3, blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2,
83                blsp_uart3, blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7,
84                blsp_uart8, blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12,
85                blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5,
86                blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10,
87                blsp_uim11, blsp_uim12, blsp11_i2c_scl_b, blsp11_i2c_sda_b,
88                blsp11_uart_rx_b, blsp11_uart_tx_b, cam_mclk0, cam_mclk1,
89                cam_mclk2, cam_mclk3, cci_async_in0, cci_async_in1,
90                cci_async_in2, cci_i2c0, cci_i2c1, cci_timer0, cci_timer1,
91                cci_timer2, cci_timer3, cci_timer4, gcc_gp1_clk_a,
92                gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a,
93                gcc_gp3_clk_b, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk,
94                gp1_clk, gps_tx, gsm_tx, hdmi_cec, hdmi_ddc, hdmi_hpd,
95                hdmi_rcv, mdp_vsync, mss_lte, nav_pps, nav_tsync,
96                qdss_cti_trig_in_a, qdss_cti_trig_in_b, qdss_cti_trig_in_c,
97                qdss_cti_trig_in_d, qdss_cti_trig_out_a, qdss_cti_trig_out_b,
98                qdss_cti_trig_out_c, qdss_cti_trig_out_d, qdss_traceclk_a,
99                qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
100                qdss_tracedata_a, qdss_tracedata_b, qua_mi2s, pci_e0, pci_e1,
101                pri_mi2s, sdc4, sec_mi2s, slimbus, spkr_i2s, ter_mi2s, tsif1,
102                tsif2, uim_batt_alarm, uim1, uim2, uim3, uim4 ]
103
104      bias-pull-down: true
105      bias-pull-up: true
106      bias-disable: true
107      drive-strength: true
108      input-enable: true
109      output-high: true
110      output-low: true
111
112    required:
113      - pins
114
115    additionalProperties: false
116
117allOf:
118  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
119
120required:
121  - compatible
122  - reg
123
124additionalProperties: false
125
126examples:
127  - |
128    #include <dt-bindings/interrupt-controller/arm-gic.h>
129
130    tlmm: pinctrl@fd510000 {
131        compatible = "qcom,msm8994-pinctrl";
132        reg = <0xfd510000 0x4000>;
133        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
134        gpio-controller;
135        gpio-ranges = <&tlmm 0 0 146>;
136        #gpio-cells = <2>;
137        interrupt-controller;
138        #interrupt-cells = <2>;
139
140        blsp1-uart2-default-state {
141            function = "blsp_uart2";
142            pins = "gpio4", "gpio5";
143            drive-strength = <16>;
144            bias-disable;
145        };
146
147        blsp1-spi1-default-state {
148            default-pins {
149                pins = "gpio0", "gpio1", "gpio3";
150                function = "blsp_spi1";
151                drive-strength = <10>;
152                bias-pull-down;
153            };
154
155            cs-pins {
156                pins = "gpio8";
157                function = "gpio";
158                drive-strength = <2>;
159                bias-disable;
160            };
161        };
162    };
163