1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,msm8916-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm MSM8916 TLMM pin controller 8 9maintainers: 10 - Bjorn Andersson <andersson@kernel.org> 11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 12 13description: 14 Top Level Mode Multiplexer pin controller in Qualcomm MSM8916 SoC. 15 16properties: 17 compatible: 18 const: qcom,msm8916-pinctrl 19 20 reg: 21 maxItems: 1 22 23 interrupts: 24 maxItems: 1 25 26 interrupt-controller: true 27 "#interrupt-cells": true 28 gpio-controller: true 29 "#gpio-cells": true 30 gpio-ranges: true 31 wakeup-parent: true 32 33 gpio-reserved-ranges: 34 minItems: 1 35 maxItems: 61 36 37 gpio-line-names: 38 maxItems: 122 39 40patternProperties: 41 "-state$": 42 oneOf: 43 - $ref: "#/$defs/qcom-msm8916-tlmm-state" 44 - patternProperties: 45 "-pins$": 46 $ref: "#/$defs/qcom-msm8916-tlmm-state" 47 additionalProperties: false 48 49$defs: 50 qcom-msm8916-tlmm-state: 51 type: object 52 description: 53 Pinctrl node's client devices use subnodes for desired pin configuration. 54 Client device subnodes use below standard properties. 55 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 56 57 properties: 58 pins: 59 description: 60 List of gpio pins affected by the properties specified in this 61 subnode. 62 items: 63 oneOf: 64 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9]|12[01])$" 65 - enum: [ qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2, 66 qdsd_data3, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, 67 sdc2_cmd, sdc2_data ] 68 minItems: 1 69 maxItems: 36 70 71 function: 72 description: 73 Specify the alternative function to be configured for the specified 74 pins. 75 76 enum: [ gpio, adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char, 77 atest_char0, atest_char1, atest_char2, atest_char3, 78 atest_combodac, atest_gpsadc0, atest_gpsadc1, atest_tsens, 79 atest_wlan0, atest_wlan1, backlight_en, bimc_dte0, bimc_dte1, 80 blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, 81 blsp_i2c6, blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2, 82 blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1, blsp_spi2_cs2, 83 blsp_spi2_cs3, blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2, 84 blsp_spi3_cs3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_uart1, 85 blsp_uart2, blsp_uim1, blsp_uim2, cam1_rst, cam1_standby, 86 cam_mclk0, cam_mclk1, cci_async, cci_i2c, cci_timer0, 87 cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out, 88 display_5v, dmic0_clk, dmic0_data, dsi_rst, ebi0_wrcdc, 89 euro_us, ext_lpass, flash_strobe, gcc_gp1_clk_a, gcc_gp1_clk_b, 90 gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, 91 gsm0_tx0, gsm0_tx1, gsm1_tx0, gsm1_tx1, gyro_accl, kpsns0, 92 kpsns1, kpsns2, ldo_en, ldo_update, mag_int, mdp_vsync, 93 modem_tsync, m_voc, nav_pps, nav_tsync, pa_indicator, pbs0, 94 pbs1, pbs2, pri_mi2s, pri_mi2s_ws, prng_rosc, 95 pwr_crypto_enabled_a, pwr_crypto_enabled_b, 96 pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a, 97 pwr_nav_enabled_b, qdss_ctitrig_in_a0, qdss_ctitrig_in_a1, 98 qdss_ctitrig_in_b0, qdss_ctitrig_in_b1, qdss_ctitrig_out_a0, 99 qdss_ctitrig_out_a1, qdss_ctitrig_out_b0, qdss_ctitrig_out_b1, 100 qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a, 101 qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, reset_n, 102 sd_card, sd_write, sec_mi2s, smb_int, ssbi_wtr0, ssbi_wtr1, 103 uim1, uim2, uim3, uim_batt, wcss_bt, wcss_fm, wcss_wlan, 104 webcam1_rst ] 105 106 bias-pull-down: true 107 bias-pull-up: true 108 bias-disable: true 109 drive-strength: true 110 input-enable: true 111 output-high: true 112 output-low: true 113 114 required: 115 - pins 116 117 additionalProperties: false 118 119allOf: 120 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 121 122required: 123 - compatible 124 - reg 125 126additionalProperties: false 127 128examples: 129 - | 130 #include <dt-bindings/interrupt-controller/arm-gic.h> 131 132 msmgpio: pinctrl@1000000 { 133 compatible = "qcom,msm8916-pinctrl"; 134 reg = <0x01000000 0x300000>; 135 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 136 gpio-controller; 137 gpio-ranges = <&msmgpio 0 0 122>; 138 #gpio-cells = <2>; 139 interrupt-controller; 140 #interrupt-cells = <2>; 141 142 blsp1-uart2-sleep-state { 143 pins = "gpio4", "gpio5"; 144 function = "gpio"; 145 146 drive-strength = <2>; 147 bias-pull-down; 148 }; 149 150 spi1-default-state { 151 spi-pins { 152 pins = "gpio0", "gpio1", "gpio3"; 153 function = "blsp_spi1"; 154 155 drive-strength = <12>; 156 bias-disable; 157 }; 158 159 cs-pins { 160 pins = "gpio2"; 161 function = "gpio"; 162 163 drive-strength = <16>; 164 bias-disable; 165 output-high; 166 }; 167 }; 168 }; 169