1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,ipq8074-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm IPQ8074 TLMM pin controller
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
13description:
14  Top Level Mode Multiplexer pin controller in Qualcomm IPQ8074 SoC.
15
16properties:
17  compatible:
18    const: qcom,ipq8074-pinctrl
19
20  reg:
21    maxItems: 1
22
23  interrupts: true
24  interrupt-controller: true
25  "#interrupt-cells": true
26  gpio-controller: true
27  "#gpio-cells": true
28  gpio-ranges: true
29  wakeup-parent: true
30
31  gpio-reserved-ranges:
32    minItems: 1
33    maxItems: 35
34
35  gpio-line-names:
36    maxItems: 70
37
38patternProperties:
39  "-state$":
40    oneOf:
41      - $ref: "#/$defs/qcom-ipq8074-tlmm-state"
42      - patternProperties:
43          "-pins$":
44            $ref: "#/$defs/qcom-ipq8074-tlmm-state"
45        additionalProperties: false
46
47$defs:
48  qcom-ipq8074-tlmm-state:
49    type: object
50    description:
51      Pinctrl node's client devices use subnodes for desired pin configuration.
52      Client device subnodes use below standard properties.
53    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
54
55    properties:
56      pins:
57        description:
58          List of gpio pins affected by the properties specified in this
59          subnode.
60        items:
61          pattern: "^gpio([0-9]|[1-6][0-9]|70)$"
62        minItems: 1
63        maxItems: 36
64
65      function:
66        description:
67          Specify the alternative function to be configured for the specified
68          pins.
69
70        enum: [ gpio, atest_char, atest_char0, atest_char1, atest_char2,
71                atest_char3, audio_rxbclk, audio_rxd, audio_rxfsync,
72                audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync,
73                audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart, blsp1_i2c,
74                blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, blsp2_uart,
75                blsp3_i2c, blsp3_spi, blsp3_spi0, blsp3_spi1, blsp3_spi2,
76                blsp3_spi3, blsp3_uart, blsp4_i2c0, blsp4_i2c1, blsp4_spi0,
77                blsp4_spi1, blsp4_uart0, blsp4_uart1, blsp5_i2c, blsp5_spi,
78                blsp5_uart, burn0, burn1, cri_trng, cri_trng0, cri_trng1, cxc0,
79                cxc1, dbg_out, gcc_plltest, gcc_tlmm, ldo_en, ldo_update, led0,
80                led1, led2, mac0_sa0, mac0_sa1, mac1_sa0, mac1_sa1, mac1_sa2,
81                mac1_sa3, mac2_sa0, mac2_sa1, mdc, mdio, pcie0_clk, pcie0_rst,
82                pcie0_wake, pcie1_clk, pcie1_rst, pcie1_wake, pcm_drx, pcm_dtx,
83                pcm_fsync, pcm_pclk, pcm_zsi0, pcm_zsi1, prng_rosc, pta1_0,
84                pta1_1, pta1_2, pta2_0, pta2_1, pta2_2, pwm0, pwm1, pwm2, pwm3,
85                qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
86                qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
87                qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
88                qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b,
89                qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
90                qdss_tracedata_b, qpic, rx0, rx1, rx2, sd_card, sd_write,
91                tsens_max, wci2a, wci2b, wci2c, wci2d ]
92
93      bias-pull-down: true
94      bias-pull-up: true
95      bias-disable: true
96      drive-strength: true
97      input-enable: true
98      output-high: true
99      output-low: true
100
101    required:
102      - pins
103
104    additionalProperties: false
105
106allOf:
107  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
108
109required:
110  - compatible
111  - reg
112
113additionalProperties: false
114
115examples:
116  - |
117    #include <dt-bindings/interrupt-controller/arm-gic.h>
118
119    tlmm: pinctrl@1000000 {
120        compatible = "qcom,ipq8074-pinctrl";
121        reg = <0x01000000 0x300000>;
122        gpio-controller;
123        #gpio-cells = <0x2>;
124        gpio-ranges = <&tlmm 0 0 70>;
125        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
126        interrupt-controller;
127        #interrupt-cells = <0x2>;
128
129        serial4-state {
130            pins = "gpio23", "gpio24";
131            function = "blsp4_uart1";
132            drive-strength = <8>;
133            bias-disable;
134        };
135    };
136