1Qualcomm IPQ8064 TLMM block
2
3Required properties:
4- compatible: "qcom,ipq8064-pinctrl"
5- reg: Should be the base address and length of the TLMM block.
6- interrupts: Should be the parent IRQ of the TLMM block.
7- interrupt-controller: Marks the device node as an interrupt controller.
8- #interrupt-cells: Should be two.
9- gpio-controller: Marks the device node as a GPIO controller.
10- #gpio-cells : Should be two.
11                The first cell is the gpio pin number and the
12                second cell is used for optional parameters.
13
14Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
15a general description of GPIO and interrupt bindings.
16
17Please refer to pinctrl-bindings.txt in this directory for details of the
18common pinctrl bindings used by client devices, including the meaning of the
19phrase "pin configuration node".
20
21Qualcomm's pin configuration nodes act as a container for an arbitrary number of
22subnodes. Each of these subnodes represents some desired configuration for a
23pin, a group, or a list of pins or groups. This configuration can include the
24mux function to select on those pin(s)/group(s), and various pin configuration
25parameters, such as pull-up, drive strength, etc.
26
27The name of each subnode is not important; all subnodes should be enumerated
28and processed purely based on their content.
29
30Each subnode only affects those parameters that are explicitly listed. In
31other words, a subnode that lists a mux function but no pin configuration
32parameters implies no information about any pin configuration parameters.
33Similarly, a pin subnode that describes a pullup parameter implies no
34information about e.g. the mux function.
35
36
37The following generic properties as defined in pinctrl-bindings.txt are valid
38to specify in a pin configuration subnode:
39
40 pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength,
41 output-low, output-high.
42
43Non-empty subnodes must specify the 'pins' property.
44
45Valid values for qcom,pins are:
46  gpio0-gpio68
47   Supports mux, bias, and drive-strength
48
49  sdc3_clk, sdc3_cmd, sdc3_data
50   Supports bias and drive-strength
51
52
53Valid values for function are:
54  mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gpio, gsbi1, gsbi2, gsbi4, gsbi5,
55  gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi7, nss_spi, sdc1,
56  spdif, nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rgmii2, sata,
57  pcie1_rst, pcie1_prsnt, pcie1_pwren_n, pcie1_pwren, pcie1_pwrflt,
58  pcie1_clk_req, pcie2_rst, pcie2_prsnt, pcie2_pwren_n, pcie2_pwren,
59  pcie2_pwrflt, pcie2_clk_req, pcie3_rst, pcie3_prsnt, pcie3_pwren_n,
60  pcie3_pwren, pcie3_pwrflt, pcie3_clk_req, ps_hold
61
62Example:
63
64	pinmux: pinctrl@800000 {
65		compatible = "qcom,ipq8064-pinctrl";
66		reg = <0x800000 0x4000>;
67
68		gpio-controller;
69		#gpio-cells = <2>;
70		interrupt-controller;
71		#interrupt-cells = <2>;
72		interrupts = <0 32 0x4>;
73
74		pinctrl-names = "default";
75		pinctrl-0 = <&gsbi5_uart_default>;
76
77		gsbi5_uart_default: gsbi5_uart_default {
78			mux {
79				pins = "gpio18", "gpio19";
80				function = "gsbi5";
81			};
82
83			tx {
84				pins = "gpio18";
85				drive-strength = <4>;
86				bias-disable;
87			};
88
89			rx {
90				pins = "gpio19";
91				drive-strength = <2>;
92				bias-pull-up;
93			};
94		};
95	};
96