1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5018-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm IPQ5018 TLMM pin controller
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
13description:
14  Top Level Mode Multiplexer pin controller in Qualcomm IPQ5018 SoC.
15
16properties:
17  compatible:
18    const: qcom,ipq5018-tlmm
19
20  reg:
21    maxItems: 1
22
23  interrupts:
24    maxItems: 1
25
26  interrupt-controller: true
27  "#interrupt-cells": true
28  gpio-controller: true
29  "#gpio-cells": true
30  gpio-ranges: true
31  wakeup-parent: true
32
33  gpio-reserved-ranges:
34    minItems: 1
35    maxItems: 24
36
37  gpio-line-names:
38    maxItems: 47
39
40patternProperties:
41  "-state$":
42    oneOf:
43      - $ref: "#/$defs/qcom-ipq5018-tlmm-state"
44      - patternProperties:
45          "-pins$":
46            $ref: "#/$defs/qcom-ipq5018-tlmm-state"
47        additionalProperties: false
48
49$defs:
50  qcom-ipq5018-tlmm-state:
51    type: object
52    description:
53      Pinctrl node's client devices use subnodes for desired pin configuration.
54      Client device subnodes use below standard properties.
55    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
56    unevaluatedProperties: false
57
58    properties:
59      pins:
60        description:
61          List of gpio pins affected by the properties specified in this
62          subnode.
63        items:
64          pattern: "^gpio([0-9]|[1-3][0-9]|4[0-6])$"
65        minItems: 1
66        maxItems: 8
67
68      function:
69        description:
70          Specify the alternative function to be configured for the specified
71          pins.
72
73        enum: [ atest_char, audio_pdm0, audio_pdm1, audio_rxbclk, audio_rxd,
74                audio_rxfsync, audio_rxmclk, audio_txbclk, audio_txd,
75                audio_txfsync, audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart0,
76                blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1,
77                blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1,
78                blsp2_spi, blsp2_spi0, blsp2_spi1, btss, burn0, burn1, cri_trng,
79                cri_trng0, cri_trng1, cxc_clk, cxc_data, dbg_out, eud_gpio,
80                gcc_plltest, gcc_tlmm, gpio, led0, led2, mac0, mac1, mdc, mdio,
81                pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, pll_test,
82                prng_rosc, pwm0, pwm1, pwm2, pwm3, qdss_cti_trig_in_a0,
83                qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
84                qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
85                qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
86                qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
87                qdss_tracedata_a, qdss_tracedata_b, qspi_clk, qspi_cs,
88                qspi_data, reset_out, sdc1_clk, sdc1_cmd, sdc1_data, wci_txd,
89                wci_rxd, wsa_swrm, wsi_clk3, wsi_data3, wsis_reset, xfem ]
90
91    required:
92      - pins
93
94required:
95  - compatible
96  - reg
97
98additionalProperties: false
99
100examples:
101  - |
102    #include <dt-bindings/interrupt-controller/arm-gic.h>
103    tlmm: pinctrl@1000000 {
104        compatible = "qcom,ipq5018-tlmm";
105        reg = <0x01000000 0x300000>;
106        gpio-controller;
107        #gpio-cells = <2>;
108        gpio-ranges = <&tlmm 0 0 47>;
109        interrupt-controller;
110        #interrupt-cells = <2>;
111        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
112
113        uart-w-state {
114            rx-pins {
115                pins = "gpio33";
116                function = "blsp1_uart1";
117                bias-pull-down;
118            };
119
120            tx-pins {
121                pins = "gpio34";
122                function = "blsp1_uart1";
123                bias-pull-down;
124            };
125        };
126    };
127...
128