1Qualcomm Atheros IPQ4019 TLMM block
2
3This is the Top Level Mode Multiplexor block found on the Qualcomm IPQ8019
4platform, it provides pinctrl, pinmux, pinconf, and gpiolib facilities.
5
6Required properties:
7- compatible: "qcom,ipq4019-pinctrl"
8- reg: Should be the base address and length of the TLMM block.
9- interrupts: Should be the parent IRQ of the TLMM block.
10- interrupt-controller: Marks the device node as an interrupt controller.
11- #interrupt-cells: Should be two.
12- gpio-controller: Marks the device node as a GPIO controller.
13- #gpio-cells : Should be two.
14                The first cell is the gpio pin number and the
15                second cell is used for optional parameters.
16
17Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
18a general description of GPIO and interrupt bindings.
19
20Please refer to pinctrl-bindings.txt in this directory for details of the
21common pinctrl bindings used by client devices, including the meaning of the
22phrase "pin configuration node".
23
24The pin configuration nodes act as a container for an abitrary number of
25subnodes. Each of these subnodes represents some desired configuration for a
26pin, a group, or a list of pins or groups. This configuration can include the
27mux function to select on those pin(s)/group(s), and various pin configuration
28parameters, such as pull-up, drive strength, etc.
29
30The name of each subnode is not important; all subnodes should be enumerated
31and processed purely based on their content.
32
33Each subnode only affects those parameters that are explicitly listed. In
34other words, a subnode that lists a mux function but no pin configuration
35parameters implies no information about any pin configuration parameters.
36Similarly, a pin subnode that describes a pullup parameter implies no
37information about e.g. the mux function.
38
39
40The following generic properties as defined in pinctrl-bindings.txt are valid
41to specify in a pin configuration subnode:
42 pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength.
43
44Non-empty subnodes must specify the 'pins' property.
45Note that not all properties are valid for all pins.
46
47
48Valid values for qcom,pins are:
49  gpio0-gpio99
50    Supports mux, bias and drive-strength
51
52Valid values for qcom,function are:
53aud_pin, audio_pwm, blsp_i2c0, blsp_i2c1, blsp_spi0, blsp_spi1, blsp_uart0,
54blsp_uart1, chip_rst, gpio, i2s_rx, i2s_spdif_in, i2s_spdif_out, i2s_td, i2s_tx,
55jtag, led0, led1, led2, led3, led4, led5, led6, led7, led8, led9, led10, led11,
56mdc, mdio, pcie, pmu, prng_rosc, qpic, rgmii, rmii, sdio, smart0, smart1,
57smart2, smart3, tm, wifi0, wifi1
58
59Example:
60
61	tlmm: pinctrl@1000000 {
62		compatible = "qcom,ipq4019-pinctrl";
63		reg = <0x1000000 0x300000>;
64
65		gpio-controller;
66		#gpio-cells = <2>;
67		interrupt-controller;
68		#interrupt-cells = <2>;
69		interrupts = <0 208 0>;
70
71		serial_pins: serial_pinmux {
72			mux {
73				pins = "gpio60", "gpio61";
74				function = "blsp_uart0";
75				bias-disable;
76			};
77		};
78	};
79