1*15dfa161SAbel Vesa# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*15dfa161SAbel Vesa%YAML 1.2 3*15dfa161SAbel Vesa--- 4*15dfa161SAbel Vesa$id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-tlmm.yaml# 5*15dfa161SAbel Vesa$schema: http://devicetree.org/meta-schemas/core.yaml# 6*15dfa161SAbel Vesa 7*15dfa161SAbel Vesatitle: Qualcomm Technologies, Inc. SM8550 TLMM block 8*15dfa161SAbel Vesa 9*15dfa161SAbel Vesamaintainers: 10*15dfa161SAbel Vesa - Abel Vesa <abel.vesa@linaro.org> 11*15dfa161SAbel Vesa 12*15dfa161SAbel Vesadescription: 13*15dfa161SAbel Vesa Top Level Mode Multiplexer pin controller in Qualcomm SM8550 SoC. 14*15dfa161SAbel Vesa 15*15dfa161SAbel VesaallOf: 16*15dfa161SAbel Vesa - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 17*15dfa161SAbel Vesa 18*15dfa161SAbel Vesaproperties: 19*15dfa161SAbel Vesa compatible: 20*15dfa161SAbel Vesa const: qcom,sm8550-tlmm 21*15dfa161SAbel Vesa 22*15dfa161SAbel Vesa reg: 23*15dfa161SAbel Vesa maxItems: 1 24*15dfa161SAbel Vesa 25*15dfa161SAbel Vesa interrupts: true 26*15dfa161SAbel Vesa interrupt-controller: true 27*15dfa161SAbel Vesa "#interrupt-cells": true 28*15dfa161SAbel Vesa gpio-controller: true 29*15dfa161SAbel Vesa 30*15dfa161SAbel Vesa gpio-reserved-ranges: 31*15dfa161SAbel Vesa minItems: 1 32*15dfa161SAbel Vesa maxItems: 105 33*15dfa161SAbel Vesa 34*15dfa161SAbel Vesa gpio-line-names: 35*15dfa161SAbel Vesa maxItems: 210 36*15dfa161SAbel Vesa 37*15dfa161SAbel Vesa "#gpio-cells": true 38*15dfa161SAbel Vesa gpio-ranges: true 39*15dfa161SAbel Vesa wakeup-parent: true 40*15dfa161SAbel Vesa 41*15dfa161SAbel VesapatternProperties: 42*15dfa161SAbel Vesa "-state$": 43*15dfa161SAbel Vesa oneOf: 44*15dfa161SAbel Vesa - $ref: "#/$defs/qcom-sm8550-tlmm-state" 45*15dfa161SAbel Vesa - patternProperties: 46*15dfa161SAbel Vesa "-pins$": 47*15dfa161SAbel Vesa $ref: "#/$defs/qcom-sm8550-tlmm-state" 48*15dfa161SAbel Vesa additionalProperties: false 49*15dfa161SAbel Vesa 50*15dfa161SAbel Vesa$defs: 51*15dfa161SAbel Vesa qcom-sm8550-tlmm-state: 52*15dfa161SAbel Vesa type: object 53*15dfa161SAbel Vesa description: 54*15dfa161SAbel Vesa Pinctrl node's client devices use subnodes for desired pin configuration. 55*15dfa161SAbel Vesa Client device subnodes use below standard properties. 56*15dfa161SAbel Vesa $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 57*15dfa161SAbel Vesa 58*15dfa161SAbel Vesa properties: 59*15dfa161SAbel Vesa pins: 60*15dfa161SAbel Vesa description: 61*15dfa161SAbel Vesa List of gpio pins affected by the properties specified in this 62*15dfa161SAbel Vesa subnode. 63*15dfa161SAbel Vesa items: 64*15dfa161SAbel Vesa oneOf: 65*15dfa161SAbel Vesa - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$" 66*15dfa161SAbel Vesa - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] 67*15dfa161SAbel Vesa minItems: 1 68*15dfa161SAbel Vesa maxItems: 36 69*15dfa161SAbel Vesa 70*15dfa161SAbel Vesa function: 71*15dfa161SAbel Vesa description: 72*15dfa161SAbel Vesa Specify the alternative function to be configured for the specified 73*15dfa161SAbel Vesa pins. 74*15dfa161SAbel Vesa enum: [ aon_cci, aoss_cti, atest_char, atest_usb, 75*15dfa161SAbel Vesa audio_ext_mclk0, audio_ext_mclk1, audio_ref_clk, 76*15dfa161SAbel Vesa cam_aon_mclk4, cam_mclk, cci_async_in, cci_i2c_scl, 77*15dfa161SAbel Vesa cci_i2c_sda, cci_timer, cmu_rng, coex_uart1_rx, 78*15dfa161SAbel Vesa coex_uart1_tx, coex_uart2_rx, coex_uart2_tx, 79*15dfa161SAbel Vesa cri_trng, dbg_out_clk, ddr_bist_complete, 80*15dfa161SAbel Vesa ddr_bist_fail, ddr_bist_start, ddr_bist_stop, 81*15dfa161SAbel Vesa ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, 82*15dfa161SAbel Vesa gcc_gp1, gcc_gp2, gcc_gp3, gpio, i2chub0_se0, 83*15dfa161SAbel Vesa i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4, 84*15dfa161SAbel Vesa i2chub0_se5, i2chub0_se6, i2chub0_se7, i2chub0_se8, 85*15dfa161SAbel Vesa i2chub0_se9, i2s0_data0, i2s0_data1, i2s0_sck, 86*15dfa161SAbel Vesa i2s0_ws, i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws, 87*15dfa161SAbel Vesa ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0_out, 88*15dfa161SAbel Vesa mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, 89*15dfa161SAbel Vesa mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, 90*15dfa161SAbel Vesa pcie0_clk_req_n, pcie1_clk_req_n, phase_flag, 91*15dfa161SAbel Vesa pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1, 92*15dfa161SAbel Vesa prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, 93*15dfa161SAbel Vesa qlink0_enable, qlink0_request, qlink0_wmss, 94*15dfa161SAbel Vesa qlink1_enable, qlink1_request, qlink1_wmss, 95*15dfa161SAbel Vesa qlink2_enable, qlink2_request, qlink2_wmss, 96*15dfa161SAbel Vesa qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, 97*15dfa161SAbel Vesa qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, 98*15dfa161SAbel Vesa qup1_se5, qup1_se6, qup1_se7, qup2_se0, 99*15dfa161SAbel Vesa qup2_se0_l0_mira, qup2_se0_l0_mirb, qup2_se0_l1_mira, 100*15dfa161SAbel Vesa qup2_se0_l1_mirb, qup2_se0_l2_mira, qup2_se0_l2_mirb, 101*15dfa161SAbel Vesa qup2_se0_l3_mira, qup2_se0_l3_mirb, qup2_se1, 102*15dfa161SAbel Vesa qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6, 103*15dfa161SAbel Vesa qup2_se7, sd_write_protect, sdc40, sdc41, sdc42, 104*15dfa161SAbel Vesa sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2, tb_trig_sdc4, 105*15dfa161SAbel Vesa tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout, 106*15dfa161SAbel Vesa tgu_ch3_trigout, tmess_prng0, tmess_prng1, tmess_prng2, 107*15dfa161SAbel Vesa tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, 108*15dfa161SAbel Vesa uim0_clk, uim0_data, uim0_present, uim0_reset, 109*15dfa161SAbel Vesa uim1_clk, uim1_data, uim1_present, uim1_reset, 110*15dfa161SAbel Vesa usb1_hs, usb_phy, vfr_0, vfr_1, vsense_trigger_mirnat ] 111*15dfa161SAbel Vesa 112*15dfa161SAbel Vesa bias-disable: true 113*15dfa161SAbel Vesa bias-pull-down: true 114*15dfa161SAbel Vesa bias-pull-up: true 115*15dfa161SAbel Vesa drive-strength: true 116*15dfa161SAbel Vesa input-enable: true 117*15dfa161SAbel Vesa output-high: true 118*15dfa161SAbel Vesa output-low: true 119*15dfa161SAbel Vesa 120*15dfa161SAbel Vesa required: 121*15dfa161SAbel Vesa - pins 122*15dfa161SAbel Vesa 123*15dfa161SAbel Vesa additionalProperties: false 124*15dfa161SAbel Vesa 125*15dfa161SAbel Vesarequired: 126*15dfa161SAbel Vesa - compatible 127*15dfa161SAbel Vesa - reg 128*15dfa161SAbel Vesa 129*15dfa161SAbel VesaadditionalProperties: false 130*15dfa161SAbel Vesa 131*15dfa161SAbel Vesaexamples: 132*15dfa161SAbel Vesa - | 133*15dfa161SAbel Vesa #include <dt-bindings/interrupt-controller/arm-gic.h> 134*15dfa161SAbel Vesa tlmm: pinctrl@f100000 { 135*15dfa161SAbel Vesa compatible = "qcom,sm8550-tlmm"; 136*15dfa161SAbel Vesa reg = <0x0f100000 0x300000>; 137*15dfa161SAbel Vesa gpio-controller; 138*15dfa161SAbel Vesa #gpio-cells = <2>; 139*15dfa161SAbel Vesa gpio-ranges = <&tlmm 0 0 211>; 140*15dfa161SAbel Vesa interrupt-controller; 141*15dfa161SAbel Vesa #interrupt-cells = <2>; 142*15dfa161SAbel Vesa interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 143*15dfa161SAbel Vesa 144*15dfa161SAbel Vesa gpio-wo-state { 145*15dfa161SAbel Vesa pins = "gpio1"; 146*15dfa161SAbel Vesa function = "gpio"; 147*15dfa161SAbel Vesa }; 148*15dfa161SAbel Vesa 149*15dfa161SAbel Vesa uart-w-state { 150*15dfa161SAbel Vesa rx-pins { 151*15dfa161SAbel Vesa pins = "gpio26"; 152*15dfa161SAbel Vesa function = "qup2_se7"; 153*15dfa161SAbel Vesa bias-pull-up; 154*15dfa161SAbel Vesa }; 155*15dfa161SAbel Vesa 156*15dfa161SAbel Vesa tx-pins { 157*15dfa161SAbel Vesa pins = "gpio27"; 158*15dfa161SAbel Vesa function = "qup2_se7"; 159*15dfa161SAbel Vesa bias-disable; 160*15dfa161SAbel Vesa }; 161*15dfa161SAbel Vesa }; 162*15dfa161SAbel Vesa }; 163*15dfa161SAbel Vesa... 164