1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-tlmm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. SM8450 TLMM block 8 9maintainers: 10 - Vinod Koul <vkoul@kernel.org> 11 12description: 13 Top Level Mode Multiplexer pin controller in Qualcomm SM8450 SoC. 14 15allOf: 16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 17 18properties: 19 compatible: 20 const: qcom,sm8450-tlmm 21 22 reg: 23 maxItems: 1 24 25 interrupts: true 26 interrupt-controller: true 27 "#interrupt-cells": true 28 gpio-controller: true 29 30 gpio-reserved-ranges: 31 minItems: 1 32 maxItems: 105 33 34 gpio-line-names: 35 maxItems: 210 36 37 "#gpio-cells": true 38 gpio-ranges: true 39 wakeup-parent: true 40 41required: 42 - compatible 43 - reg 44 45additionalProperties: false 46 47patternProperties: 48 "-state$": 49 oneOf: 50 - $ref: "#/$defs/qcom-sm8450-tlmm-state" 51 - patternProperties: 52 "-pins$": 53 $ref: "#/$defs/qcom-sm8450-tlmm-state" 54 additionalProperties: false 55 56$defs: 57 qcom-sm8450-tlmm-state: 58 type: object 59 description: 60 Pinctrl node's client devices use subnodes for desired pin configuration. 61 Client device subnodes use below standard properties. 62 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 63 64 properties: 65 pins: 66 description: 67 List of gpio pins affected by the properties specified in this 68 subnode. 69 items: 70 oneOf: 71 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$" 72 - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] 73 minItems: 1 74 maxItems: 36 75 76 function: 77 description: 78 Specify the alternative function to be configured for the specified 79 pins. 80 enum: [ aon_cam, atest_char, atest_usb, audio_ref, cam_mclk, cci_async, 81 cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng, 82 cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, 83 ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1, gcc_gp2, gcc_gp3, 84 gpio, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1, 85 mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck, 86 mi2s0_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, 87 mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, 88 mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, 89 mss_grfc7, mss_grfc8, mss_grfc9, nav, pcie0_clkreqn, 90 pcie1_clkreqn, phase_flag, pll_bist, pll_clk, pri_mi2s, 91 prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, qlink0_request, 92 qlink0_wmss, qlink1_enable, qlink1_request, qlink1_wmss, 93 qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1, 94 qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, 95 qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19, qup2, 96 qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, 97 qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk, 98 sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, 99 tgu_ch3, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3, 100 tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present, 101 uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset, 102 usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ] 103 104 bias-disable: true 105 bias-pull-down: true 106 bias-pull-up: true 107 drive-strength: true 108 input-enable: true 109 output-high: true 110 output-low: true 111 112 required: 113 - pins 114 115 additionalProperties: false 116 117examples: 118 - | 119 #include <dt-bindings/interrupt-controller/arm-gic.h> 120 pinctrl@f100000 { 121 compatible = "qcom,sm8450-tlmm"; 122 reg = <0x0f100000 0x300000>; 123 gpio-controller; 124 #gpio-cells = <2>; 125 gpio-ranges = <&tlmm 0 0 211>; 126 interrupt-controller; 127 #interrupt-cells = <2>; 128 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 129 130 gpio-wo-state { 131 pins = "gpio1"; 132 function = "gpio"; 133 }; 134 135 uart-w-state { 136 rx-pins { 137 pins = "gpio26"; 138 function = "qup7"; 139 bias-pull-up; 140 }; 141 142 tx-pins { 143 pins = "gpio27"; 144 function = "qup7"; 145 bias-disable; 146 }; 147 }; 148 }; 149... 150