1*7ddfbb41SKrzysztof Kozlowski# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*7ddfbb41SKrzysztof Kozlowski%YAML 1.2
3*7ddfbb41SKrzysztof Kozlowski---
4*7ddfbb41SKrzysztof Kozlowski$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-tlmm.yaml#
5*7ddfbb41SKrzysztof Kozlowski$schema: http://devicetree.org/meta-schemas/core.yaml#
6*7ddfbb41SKrzysztof Kozlowski
7*7ddfbb41SKrzysztof Kozlowskititle: Qualcomm Technologies, Inc. SM8450 TLMM block
8*7ddfbb41SKrzysztof Kozlowski
9*7ddfbb41SKrzysztof Kozlowskimaintainers:
10*7ddfbb41SKrzysztof Kozlowski  - Vinod Koul <vkoul@kernel.org>
11*7ddfbb41SKrzysztof Kozlowski
12*7ddfbb41SKrzysztof Kozlowskidescription:
13*7ddfbb41SKrzysztof Kozlowski  Top Level Mode Multiplexer pin controller in Qualcomm SM8450 SoC.
14*7ddfbb41SKrzysztof Kozlowski
15*7ddfbb41SKrzysztof KozlowskiallOf:
16*7ddfbb41SKrzysztof Kozlowski  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17*7ddfbb41SKrzysztof Kozlowski
18*7ddfbb41SKrzysztof Kozlowskiproperties:
19*7ddfbb41SKrzysztof Kozlowski  compatible:
20*7ddfbb41SKrzysztof Kozlowski    const: qcom,sm8450-tlmm
21*7ddfbb41SKrzysztof Kozlowski
22*7ddfbb41SKrzysztof Kozlowski  reg:
23*7ddfbb41SKrzysztof Kozlowski    maxItems: 1
24*7ddfbb41SKrzysztof Kozlowski
25*7ddfbb41SKrzysztof Kozlowski  interrupts: true
26*7ddfbb41SKrzysztof Kozlowski  interrupt-controller: true
27*7ddfbb41SKrzysztof Kozlowski  "#interrupt-cells": true
28*7ddfbb41SKrzysztof Kozlowski  gpio-controller: true
29*7ddfbb41SKrzysztof Kozlowski
30*7ddfbb41SKrzysztof Kozlowski  gpio-reserved-ranges:
31*7ddfbb41SKrzysztof Kozlowski    minItems: 1
32*7ddfbb41SKrzysztof Kozlowski    maxItems: 105
33*7ddfbb41SKrzysztof Kozlowski
34*7ddfbb41SKrzysztof Kozlowski  gpio-line-names:
35*7ddfbb41SKrzysztof Kozlowski    maxItems: 209
36*7ddfbb41SKrzysztof Kozlowski
37*7ddfbb41SKrzysztof Kozlowski  "#gpio-cells": true
38*7ddfbb41SKrzysztof Kozlowski  gpio-ranges: true
39*7ddfbb41SKrzysztof Kozlowski  wakeup-parent: true
40*7ddfbb41SKrzysztof Kozlowski
41*7ddfbb41SKrzysztof Kozlowskirequired:
42*7ddfbb41SKrzysztof Kozlowski  - compatible
43*7ddfbb41SKrzysztof Kozlowski  - reg
44*7ddfbb41SKrzysztof Kozlowski
45*7ddfbb41SKrzysztof KozlowskiadditionalProperties: false
46*7ddfbb41SKrzysztof Kozlowski
47*7ddfbb41SKrzysztof KozlowskipatternProperties:
48*7ddfbb41SKrzysztof Kozlowski  "-state$":
49*7ddfbb41SKrzysztof Kozlowski    oneOf:
50*7ddfbb41SKrzysztof Kozlowski      - $ref: "#/$defs/qcom-sm8450-tlmm-state"
51*7ddfbb41SKrzysztof Kozlowski      - patternProperties:
52*7ddfbb41SKrzysztof Kozlowski          "-pins$":
53*7ddfbb41SKrzysztof Kozlowski            $ref: "#/$defs/qcom-sm8450-tlmm-state"
54*7ddfbb41SKrzysztof Kozlowski        additionalProperties: false
55*7ddfbb41SKrzysztof Kozlowski
56*7ddfbb41SKrzysztof Kozlowski$defs:
57*7ddfbb41SKrzysztof Kozlowski  qcom-sm8450-tlmm-state:
58*7ddfbb41SKrzysztof Kozlowski    type: object
59*7ddfbb41SKrzysztof Kozlowski    description:
60*7ddfbb41SKrzysztof Kozlowski      Pinctrl node's client devices use subnodes for desired pin configuration.
61*7ddfbb41SKrzysztof Kozlowski      Client device subnodes use below standard properties.
62*7ddfbb41SKrzysztof Kozlowski    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
63*7ddfbb41SKrzysztof Kozlowski
64*7ddfbb41SKrzysztof Kozlowski    properties:
65*7ddfbb41SKrzysztof Kozlowski      pins:
66*7ddfbb41SKrzysztof Kozlowski        description:
67*7ddfbb41SKrzysztof Kozlowski          List of gpio pins affected by the properties specified in this
68*7ddfbb41SKrzysztof Kozlowski          subnode.
69*7ddfbb41SKrzysztof Kozlowski        items:
70*7ddfbb41SKrzysztof Kozlowski          oneOf:
71*7ddfbb41SKrzysztof Kozlowski            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
72*7ddfbb41SKrzysztof Kozlowski            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
73*7ddfbb41SKrzysztof Kozlowski        minItems: 1
74*7ddfbb41SKrzysztof Kozlowski        maxItems: 36
75*7ddfbb41SKrzysztof Kozlowski
76*7ddfbb41SKrzysztof Kozlowski      function:
77*7ddfbb41SKrzysztof Kozlowski        description:
78*7ddfbb41SKrzysztof Kozlowski          Specify the alternative function to be configured for the specified
79*7ddfbb41SKrzysztof Kozlowski          pins.
80*7ddfbb41SKrzysztof Kozlowski        enum: [ aon_cam, atest_char, atest_usb, audio_ref, cam_mclk, cci_async,
81*7ddfbb41SKrzysztof Kozlowski                cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng,
82*7ddfbb41SKrzysztof Kozlowski                cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
83*7ddfbb41SKrzysztof Kozlowski                ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1, gcc_gp2, gcc_gp3,
84*7ddfbb41SKrzysztof Kozlowski                gpio, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1,
85*7ddfbb41SKrzysztof Kozlowski                mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck,
86*7ddfbb41SKrzysztof Kozlowski                mi2s0_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws,
87*7ddfbb41SKrzysztof Kozlowski                mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
88*7ddfbb41SKrzysztof Kozlowski                mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6,
89*7ddfbb41SKrzysztof Kozlowski                mss_grfc7, mss_grfc8, mss_grfc9, nav, pcie0_clkreqn,
90*7ddfbb41SKrzysztof Kozlowski                pcie1_clkreqn, phase_flag, pll_bist, pll_clk, pri_mi2s,
91*7ddfbb41SKrzysztof Kozlowski                prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, qlink0_request,
92*7ddfbb41SKrzysztof Kozlowski                qlink0_wmss, qlink1_enable, qlink1_request, qlink1_wmss,
93*7ddfbb41SKrzysztof Kozlowski                qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1,
94*7ddfbb41SKrzysztof Kozlowski                qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11,
95*7ddfbb41SKrzysztof Kozlowski                qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19, qup2,
96*7ddfbb41SKrzysztof Kozlowski                qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4,
97*7ddfbb41SKrzysztof Kozlowski                qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk,
98*7ddfbb41SKrzysztof Kozlowski                sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2,
99*7ddfbb41SKrzysztof Kozlowski                tgu_ch3, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
100*7ddfbb41SKrzysztof Kozlowski                tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present,
101*7ddfbb41SKrzysztof Kozlowski                uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset,
102*7ddfbb41SKrzysztof Kozlowski                usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ]
103*7ddfbb41SKrzysztof Kozlowski
104*7ddfbb41SKrzysztof Kozlowski      bias-disable: true
105*7ddfbb41SKrzysztof Kozlowski      bias-pull-down: true
106*7ddfbb41SKrzysztof Kozlowski      bias-pull-up: true
107*7ddfbb41SKrzysztof Kozlowski      drive-strength: true
108*7ddfbb41SKrzysztof Kozlowski      input-enable: true
109*7ddfbb41SKrzysztof Kozlowski      output-high: true
110*7ddfbb41SKrzysztof Kozlowski      output-low: true
111*7ddfbb41SKrzysztof Kozlowski
112*7ddfbb41SKrzysztof Kozlowski    required:
113*7ddfbb41SKrzysztof Kozlowski      - pins
114*7ddfbb41SKrzysztof Kozlowski
115*7ddfbb41SKrzysztof Kozlowski    additionalProperties: false
116*7ddfbb41SKrzysztof Kozlowski
117*7ddfbb41SKrzysztof Kozlowskiexamples:
118*7ddfbb41SKrzysztof Kozlowski  - |
119*7ddfbb41SKrzysztof Kozlowski    #include <dt-bindings/interrupt-controller/arm-gic.h>
120*7ddfbb41SKrzysztof Kozlowski    pinctrl@f100000 {
121*7ddfbb41SKrzysztof Kozlowski        compatible = "qcom,sm8450-tlmm";
122*7ddfbb41SKrzysztof Kozlowski        reg = <0x0f100000 0x300000>;
123*7ddfbb41SKrzysztof Kozlowski        gpio-controller;
124*7ddfbb41SKrzysztof Kozlowski        #gpio-cells = <2>;
125*7ddfbb41SKrzysztof Kozlowski        gpio-ranges = <&tlmm 0 0 211>;
126*7ddfbb41SKrzysztof Kozlowski        interrupt-controller;
127*7ddfbb41SKrzysztof Kozlowski        #interrupt-cells = <2>;
128*7ddfbb41SKrzysztof Kozlowski        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
129*7ddfbb41SKrzysztof Kozlowski
130*7ddfbb41SKrzysztof Kozlowski        gpio-wo-state {
131*7ddfbb41SKrzysztof Kozlowski            pins = "gpio1";
132*7ddfbb41SKrzysztof Kozlowski            function = "gpio";
133*7ddfbb41SKrzysztof Kozlowski        };
134*7ddfbb41SKrzysztof Kozlowski
135*7ddfbb41SKrzysztof Kozlowski        uart-w-state {
136*7ddfbb41SKrzysztof Kozlowski            rx-pins {
137*7ddfbb41SKrzysztof Kozlowski                pins = "gpio26";
138*7ddfbb41SKrzysztof Kozlowski                function = "qup7";
139*7ddfbb41SKrzysztof Kozlowski                bias-pull-up;
140*7ddfbb41SKrzysztof Kozlowski            };
141*7ddfbb41SKrzysztof Kozlowski
142*7ddfbb41SKrzysztof Kozlowski            tx-pins {
143*7ddfbb41SKrzysztof Kozlowski                pins = "gpio27";
144*7ddfbb41SKrzysztof Kozlowski                function = "qup7";
145*7ddfbb41SKrzysztof Kozlowski                bias-disable;
146*7ddfbb41SKrzysztof Kozlowski            };
147*7ddfbb41SKrzysztof Kozlowski        };
148*7ddfbb41SKrzysztof Kozlowski    };
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