1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS) 8 Low Power Island (LPI) TLMM block 9 10maintainers: 11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> 12 13description: | 14 This binding describes the Top Level Mode Multiplexer block found in the 15 LPASS LPI IP on most Qualcomm SoCs 16 17properties: 18 compatible: 19 const: qcom,sm8250-lpass-lpi-pinctrl 20 21 reg: 22 minItems: 2 23 maxItems: 2 24 25 clocks: 26 items: 27 - description: LPASS Core voting clock 28 - description: LPASS Audio voting clock 29 30 clock-names: 31 items: 32 - const: core 33 - const: audio 34 35 gpio-controller: true 36 37 '#gpio-cells': 38 description: Specifying the pin number and flags, as defined in 39 include/dt-bindings/gpio/gpio.h 40 const: 2 41 42 gpio-ranges: 43 maxItems: 1 44 45patternProperties: 46 "-state$": 47 oneOf: 48 - $ref: "#/$defs/qcom-sm8250-lpass-state" 49 - patternProperties: 50 "-pins$": 51 $ref: "#/$defs/qcom-sm8250-lpass-state" 52 additionalProperties: false 53 54$defs: 55 qcom-sm8250-lpass-state: 56 type: object 57 description: 58 Pinctrl node's client devices use subnodes for desired pin configuration. 59 Client device subnodes use below standard properties. 60 $ref: "/schemas/pinctrl/pincfg-node.yaml" 61 62 properties: 63 pins: 64 description: 65 List of gpio pins affected by the properties specified in this 66 subnode. 67 items: 68 oneOf: 69 - pattern: "^gpio([0-9]|[1-9][0-9])$" 70 minItems: 1 71 maxItems: 14 72 73 function: 74 enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws, 75 qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk, 76 dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data, 77 i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk, 78 dmic3_data, i2s2_data ] 79 description: 80 Specify the alternative function to be configured for the specified 81 pins. 82 83 drive-strength: 84 enum: [2, 4, 6, 8, 10, 12, 14, 16] 85 default: 2 86 description: 87 Selects the drive strength for the specified pins, in mA. 88 89 slew-rate: 90 enum: [0, 1, 2, 3] 91 default: 0 92 description: | 93 0: No adjustments 94 1: Higher Slew rate (faster edges) 95 2: Lower Slew rate (slower edges) 96 3: Reserved (No adjustments) 97 98 bias-pull-down: true 99 bias-pull-up: true 100 bias-bus-hold: true 101 bias-disable: true 102 input-enable: true 103 output-high: true 104 output-low: true 105 106 required: 107 - pins 108 - function 109 110 additionalProperties: false 111 112allOf: 113 - $ref: "pinctrl.yaml#" 114 115required: 116 - compatible 117 - reg 118 - clocks 119 - clock-names 120 - gpio-controller 121 - '#gpio-cells' 122 - gpio-ranges 123 124additionalProperties: false 125 126examples: 127 - | 128 #include <dt-bindings/sound/qcom,q6afe.h> 129 lpi_tlmm: pinctrl@33c0000 { 130 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 131 reg = <0x33c0000 0x20000>, 132 <0x3550000 0x10000>; 133 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 134 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 135 clock-names = "core", "audio"; 136 gpio-controller; 137 #gpio-cells = <2>; 138 gpio-ranges = <&lpi_tlmm 0 0 14>; 139 140 wsa-swr-active-state { 141 clk-pins { 142 pins = "gpio10"; 143 function = "wsa_swr_clk"; 144 drive-strength = <2>; 145 slew-rate = <1>; 146 bias-disable; 147 }; 148 149 data-pins { 150 pins = "gpio11"; 151 function = "wsa_swr_data"; 152 drive-strength = <2>; 153 slew-rate = <1>; 154 }; 155 }; 156 157 tx-swr-sleep-clk-state { 158 pins = "gpio0"; 159 function = "swr_tx_clk"; 160 drive-strength = <2>; 161 bias-pull-down; 162 }; 163 }; 164