1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-tlmm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. SM6350 TLMM block 8 9maintainers: 10 - Konrad Dybcio <konrad.dybcio@somainline.org> 11 12description: 13 Top Level Mode Multiplexer pin controller in Qualcomm SM6350 SoC. 14 15allOf: 16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 17 18properties: 19 compatible: 20 const: qcom,sm6350-tlmm 21 22 reg: 23 maxItems: 1 24 25 interrupts: true 26 interrupt-controller: true 27 "#interrupt-cells": true 28 gpio-controller: true 29 30 gpio-reserved-ranges: 31 minItems: 1 32 maxItems: 78 33 34 gpio-line-names: 35 maxItems: 156 36 37 "#gpio-cells": true 38 gpio-ranges: true 39 wakeup-parent: true 40 41required: 42 - compatible 43 - reg 44 45additionalProperties: false 46 47patternProperties: 48 "-state$": 49 oneOf: 50 - $ref: "#/$defs/qcom-sm6350-tlmm-state" 51 - patternProperties: 52 "-pins$": 53 $ref: "#/$defs/qcom-sm6350-tlmm-state" 54 additionalProperties: false 55 56$defs: 57 qcom-sm6350-tlmm-state: 58 type: object 59 description: 60 Pinctrl node's client devices use subnodes for desired pin configuration. 61 Client device subnodes use below standard properties. 62 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 63 64 properties: 65 pins: 66 description: 67 List of gpio pins affected by the properties specified in this 68 subnode. 69 items: 70 oneOf: 71 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$" 72 - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] 73 minItems: 1 74 maxItems: 36 75 76 function: 77 description: 78 Specify the alternative function to be configured for the specified 79 pins. 80 81 enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1, atest_char2, 82 atest_char3, atest_tsens, atest_tsens2, atest_usb1, atest_usb10, atest_usb11, 83 atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21, atest_usb22, 84 atest_usb23, audio_ref, btfm_slimbus, cam_mclk0, cam_mclk1, cam_mclk2, cam_mclk3, 85 cam_mclk4, cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, 86 cci_timer4, cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, 87 dp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0, gp_pdm1, gp_pdm2, gpio, 88 gps_tx, ibi_i3c, jitter_bist, ldo_en, ldo_update, lpass_ext, m_voc, mclk, 89 mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0, mi2s_1, mi2s_2, 90 mss_lte, nav_gpio, nav_pps, pa_indicator, pcie0_clk, phase_flag0, phase_flag1, 91 phase_flag10, phase_flag11, phase_flag12, phase_flag13, phase_flag14, phase_flag15, 92 phase_flag16, phase_flag17, phase_flag18, phase_flag19, phase_flag2, phase_flag20, 93 phase_flag21, phase_flag22, phase_flag23, phase_flag24, phase_flag25, phase_flag26, 94 phase_flag27, phase_flag28, phase_flag29, phase_flag3, phase_flag30, phase_flag31, 95 phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8, phase_flag9, 96 pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti, qdss_gpio, qdss_gpio0, 97 qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14, 98 qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, 99 qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable, qlink0_request, qlink0_wmss, 100 qlink1_enable, qlink1_request, qlink1_wmss, qup00, qup01, qup02, qup10, qup11, 101 qup12, qup13_f1, qup13_f2, qup14, rffe0_clk, rffe0_data, rffe1_clk, rffe1_data, 102 rffe2_clk, rffe2_data, rffe3_clk, rffe3_data, rffe4_clk, rffe4_data, sd_write, 103 sdc1_tb, sdc2_tb, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, 104 tsense_pwm2, uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, 105 uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, 106 wlan2_adc0, wlan2_adc1, ] 107 108 109 bias-disable: true 110 bias-pull-down: true 111 bias-pull-up: true 112 drive-strength: true 113 input-enable: true 114 output-high: true 115 output-low: true 116 117 required: 118 - pins 119 120 additionalProperties: false 121 122examples: 123 - | 124 #include <dt-bindings/interrupt-controller/arm-gic.h> 125 pinctrl@f100000 { 126 compatible = "qcom,sm6350-tlmm"; 127 reg = <0x0f100000 0x300000>; 128 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 129 gpio-controller; 130 #gpio-cells = <2>; 131 interrupt-controller; 132 #interrupt-cells = <2>; 133 gpio-ranges = <&tlmm 0 0 157>; 134 135 gpio-wo-subnode-state { 136 pins = "gpio1"; 137 function = "gpio"; 138 }; 139 140 uart-w-subnodes-state { 141 rx-pins { 142 pins = "gpio25"; 143 function = "qup13_f2"; 144 bias-disable; 145 }; 146 147 tx-pins { 148 pins = "gpio26"; 149 function = "qup13_f2"; 150 bias-disable; 151 }; 152 }; 153 }; 154... 155