1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,sdm845-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SDM845 TLMM pin controller 8 9maintainers: 10 - Bjorn Andersson <andersson@kernel.org> 11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 12 13description: 14 Top Level Mode Multiplexer pin controller in Qualcomm SDM845 SoC. 15 16allOf: 17 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 18 19properties: 20 compatible: 21 const: qcom,sdm845-pinctrl 22 23 reg: 24 maxItems: 1 25 26 interrupts: true 27 interrupt-controller: true 28 "#interrupt-cells": true 29 gpio-controller: true 30 31 gpio-reserved-ranges: 32 minItems: 1 33 maxItems: 75 34 35 gpio-line-names: 36 maxItems: 150 37 38 "#gpio-cells": true 39 gpio-ranges: true 40 wakeup-parent: true 41 42patternProperties: 43 "-state$": 44 oneOf: 45 - $ref: "#/$defs/qcom-sdm845-tlmm-state" 46 - patternProperties: 47 "-pins$": 48 $ref: "#/$defs/qcom-sdm845-tlmm-state" 49 additionalProperties: false 50 51 "-hog(-[0-9]+)?$": 52 required: 53 - gpio-hog 54 55$defs: 56 qcom-sdm845-tlmm-state: 57 type: object 58 description: 59 Pinctrl node's client devices use subnodes for desired pin configuration. 60 Client device subnodes use below standard properties. 61 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 62 63 properties: 64 pins: 65 description: 66 List of gpio pins affected by the properties specified in this 67 subnode. 68 items: 69 oneOf: 70 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$" 71 - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] 72 minItems: 1 73 maxItems: 36 74 75 function: 76 description: 77 Specify the alternative function to be configured for the specified 78 pins. 79 enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2, 80 atest_usb1, atest_usb10, atest_usb11, atest_usb12, atest_usb13, 81 atest_usb2, atest_usb20, atest_usb21, atest_usb22, atest_usb23, 82 audio_ref, btfm_slimbus, cam_mclk, cci_async, cci_i2c, 83 cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, 84 cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, 85 ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, 86 gcc_gp2, gcc_gp3, gpio, jitter_bist, ldo_en, ldo_update, 87 lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, 88 mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator, pci_e0, 89 pci_e1, phase_flag, pll_bist, pll_bypassnl, pll_reset, 90 pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti, qlink_enable, 91 qlink_request, qspi_clk, qspi_cs, qspi_data, qua_mi2s, qup0, 92 qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3, 93 qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, 94 sdc4_clk, sdc4_cmd, sdc4_data, sd_write, sec_mi2s, sp_cmu, 95 spkr_i2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, 96 tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en, 97 tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en, 98 tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present, 99 uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, 100 uim_batt, usb_phy, vfr_1, vsense_trigger, wlan1_adc0, 101 wlan1_adc1, wlan2_adc0, wlan2_adc1] 102 103 bias-disable: true 104 bias-pull-down: true 105 bias-pull-up: true 106 drive-strength: true 107 input-enable: true 108 output-high: true 109 output-low: true 110 111 required: 112 - pins 113 114 additionalProperties: false 115 116required: 117 - compatible 118 - reg 119 120additionalProperties: false 121 122examples: 123 - | 124 #include <dt-bindings/gpio/gpio.h> 125 #include <dt-bindings/interrupt-controller/arm-gic.h> 126 127 pinctrl@3400000 { 128 compatible = "qcom,sdm845-pinctrl"; 129 reg = <0x03400000 0xc00000>; 130 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 131 gpio-controller; 132 #gpio-cells = <2>; 133 interrupt-controller; 134 #interrupt-cells = <2>; 135 gpio-ranges = <&tlmm 0 0 151>; 136 wakeup-parent = <&pdc_intc>; 137 138 ap-suspend-l-hog { 139 gpio-hog; 140 gpios = <126 GPIO_ACTIVE_LOW>; 141 output-low; 142 }; 143 144 cci0-default-state { 145 pins = "gpio17", "gpio18"; 146 function = "cci_i2c"; 147 148 bias-pull-up; 149 drive-strength = <2>; 150 }; 151 152 cam0-default-state { 153 rst-pins { 154 pins = "gpio9"; 155 function = "gpio"; 156 157 drive-strength = <16>; 158 bias-disable; 159 }; 160 161 mclk0-pins { 162 pins = "gpio13"; 163 function = "cam_mclk"; 164 165 drive-strength = <16>; 166 bias-disable; 167 }; 168 }; 169 }; 170