xref: /openbmc/linux/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-tlmm.yaml (revision e1a31f98)

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sc8180x-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. SC8180X TLMM block

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm SC8180X SoC.

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    const: qcom,sc8180x-tlmm

  reg:
    maxItems: 3

  reg-names:
    items:
      - const: west
      - const: east
      - const: south

  interrupts: true
  interrupt-controller: true
  '#interrupt-cells': true
  gpio-controller: true
  gpio-reserved-ranges: true
  '#gpio-cells': true
  gpio-ranges: true
  wakeup-parent: true

required:
  - compatible
  - reg
  - reg-names

additionalProperties: false

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sc8180x-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sc8180x-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sc8180x-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-8][0-9])$"
            - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
        minItems: 1
        maxItems: 16

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens,
                atest_tsens2, atest_usb0, atest_usb1, atest_usb2, atest_usb3,
                atest_usb4, audio_ref, btfm_slimbus, cam_mclk, cci_async,
                cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
                cci_timer4, cci_timer5, cci_timer6, cci_timer7, cci_timer8,
                cci_timer9, cri_trng, dbg_out, ddr_bist, ddr_pxi, debug_hot,
                dp_hot, edp_hot, edp_lcd, emac_phy, emac_pps, gcc_gp1, gcc_gp2,
                gcc_gp3, gcc_gp4, gcc_gp5, gpio, gps, grfc, hs1_mi2s, hs2_mi2s,
                hs3_mi2s, jitter_bist, lpass_slimbus, m_voc, mdp_vsync,
                mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4,
                mdp_vsync5, mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1,
                pci_e2, pci_e3, phase_flag, pll_bist, pll_bypassnl, pll_reset,
                pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss_gpio, qlink,
                qspi0, qspi0_clk, qspi0_cs, qspi1, qspi1_clk, qspi1_cs,
                qua_mi2s, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
                qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
                qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii, sd_write, sdc4,
                sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu,
                tsense_pwm1, tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt,
                usb0_phy, usb1_phy, usb2phy_ac, vfr_1, vsense_trigger,
                wlan1_adc, wlan2_adc, wmss_reset ]

      bias-disable: true
      bias-pull-down: true
      bias-pull-up: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    pinctrl@3100000 {
        compatible = "qcom,sc8180x-tlmm";
        reg = <0x03100000 0x300000>,
              <0x03500000 0x700000>,
              <0x03d00000 0x300000>;
        reg-names = "west", "east", "south";
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        gpio-ranges = <&tlmm 0 0 190>;

        gpio-wo-subnode-state {
            pins = "gpio1";
            function = "gpio";
        };

        uart-w-subnodes-state {
            rx-pins {
                pins = "gpio4";
                function = "qup6";
                bias-pull-up;
            };

            tx-pins {
                pins = "gpio5";
                function = "qup6";
                bias-disable;
            };
        };
    };
...