1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,msm8660-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm MSM8660 TLMM pin controller
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
13description:
14  Top Level Mode Multiplexer pin controller in Qualcomm MSM8660 SoC.
15
16properties:
17  compatible:
18    const: qcom,msm8660-pinctrl
19
20  reg:
21    maxItems: 1
22
23  interrupts:
24    maxItems: 1
25
26  interrupt-controller: true
27  "#interrupt-cells": true
28  gpio-controller: true
29  "#gpio-cells": true
30  gpio-ranges: true
31  wakeup-parent: true
32
33  gpio-reserved-ranges:
34    minItems: 1
35    maxItems: 86
36
37  gpio-line-names:
38    maxItems: 173
39
40patternProperties:
41  "-state$":
42    oneOf:
43      - $ref: "#/$defs/qcom-msm8660-tlmm-state"
44      - patternProperties:
45          "-pins$":
46            $ref: "#/$defs/qcom-msm8660-tlmm-state"
47        additionalProperties: false
48
49$defs:
50  qcom-msm8660-tlmm-state:
51    type: object
52    description:
53      Pinctrl node's client devices use subnodes for desired pin configuration.
54      Client device subnodes use below standard properties.
55    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
56    unevaluatedProperties: false
57
58    properties:
59      pins:
60        description:
61          List of gpio pins affected by the properties specified in this
62          subnode.
63        items:
64          oneOf:
65            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-2])$"
66            - enum: [ sdc3_clk, sdc3_cmd, sdc3_data, sdc4_clk, sdc4_cmd, sdc4_data ]
67        minItems: 1
68        maxItems: 36
69
70      function:
71        description:
72          Specify the alternative function to be configured for the specified
73          pins.
74
75        enum: [ gpio, cam_mclk, dsub, ext_gps, gp_clk_0a, gp_clk_0b, gp_clk_1a,
76                gp_clk_1b, gp_clk_2a, gp_clk_2b, gp_mn, gsbi1, gsbi1_spi_cs1_n,
77                gsbi1_spi_cs2a_n, gsbi1_spi_cs2b_n, gsbi1_spi_cs3_n, gsbi2,
78                gsbi2_spi_cs1_n, gsbi2_spi_cs2_n, gsbi2_spi_cs3_n, gsbi3,
79                gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n, gsbi4,
80                gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12,
81                hdmi, i2s, lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2,
82                sdc5, tsif1, tsif2, usb_fs1, usb_fs1_oe_n, usb_fs2,
83                usb_fs2_oe_n, vfe, vsens_alarm, ebi2, ebi2cs ]
84
85    required:
86      - pins
87
88allOf:
89  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
90
91required:
92  - compatible
93  - reg
94
95additionalProperties: false
96
97examples:
98  - |
99    #include <dt-bindings/interrupt-controller/arm-gic.h>
100    tlmm: pinctrl@800000 {
101        compatible = "qcom,msm8660-pinctrl";
102        reg = <0x800000 0x4000>;
103
104        gpio-controller;
105        gpio-ranges = <&tlmm 0 0 173>;
106        #gpio-cells = <2>;
107        interrupts = <0 16 0x4>;
108        interrupt-controller;
109        #interrupt-cells = <2>;
110
111        gsbi3-i2c-state {
112            pins = "gpio43", "gpio44";
113            function = "gsbi3";
114            drive-strength = <8>;
115            bias-disable;
116        };
117    };
118