1Microchip MCP2308/MCP23S08/MCP23017/MCP23S17 driver for
28-/16-bit I/O expander with serial interface (I2C/SPI)
3
4Required properties:
5- compatible : Should be
6    - "mcp,mcp23s08" (DEPRECATED) for  8 GPIO SPI version
7    - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version
8    - "mcp,mcp23008" (DEPRECATED) for  8 GPIO I2C version or
9    - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip
10
11    - "microchip,mcp23s08" for  8 GPIO SPI version
12    - "microchip,mcp23s17" for 16 GPIO SPI version
13    - "microchip,mcp23s18" for 16 GPIO SPI version
14    - "microchip,mcp23008" for  8 GPIO I2C version or
15    - "microchip,mcp23017" for 16 GPIO I2C version of the chip
16    - "microchip,mcp23018" for 16 GPIO I2C version
17    NOTE: Do not use the old mcp prefix any more. It is deprecated and will be
18    removed.
19- #gpio-cells : Should be two.
20  - first cell is the pin number
21  - second cell is used to specify flags. Flags are currently unused.
22- gpio-controller : Marks the device node as a GPIO controller.
23- reg : For an address on its bus. I2C uses this a the I2C address of the chip.
24        SPI uses this to specify the chipselect line which the chip is
25        connected to. The driver and the SPI variant of the chip support
26        multiple chips on the same chipselect. Have a look at
27        microchip,spi-present-mask below.
28
29Required device specific properties (only for SPI chips):
30- mcp,spi-present-mask (DEPRECATED)
31- microchip,spi-present-mask : This is a present flag, that makes only sense for SPI
32        chips - as the name suggests. Multiple SPI chips can share the same
33        SPI chipselect. Set a bit in bit0-7 in this mask to 1 if there is a
34        chip connected with the corresponding spi address set. For example if
35        you have a chip with address 3 connected, you have to set bit3 to 1,
36        which is 0x08. mcp23s08 chip variant only supports bits 0-3. It is not
37        possible to mix mcp23s08 and mcp23s17 on the same chipselect. Set at
38        least one bit to 1 for SPI chips.
39    NOTE: Do not use the old mcp prefix any more. It is deprecated and will be
40    removed.
41- spi-max-frequency = The maximum frequency this chip is able to handle
42
43Optional properties:
44- #interrupt-cells : Should be two.
45  - first cell is the pin number
46  - second cell is used to specify flags.
47- interrupt-controller: Marks the device node as a interrupt controller.
48- drive-open-drain: Sets the ODR flag in the IOCON register. This configures
49        the IRQ output as open drain active low.
50
51Optional device specific properties:
52- microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices
53        with two interrupt outputs (these are the devices ending with 17 and
54        those that have 16 IOs) have two IO banks: IO 0-7 form bank 1 and
55        IO 8-15 are bank 2. These chips have two different interrupt outputs:
56        One for bank 1 and another for bank 2. If irq-mirror is set, both
57        interrupts are generated regardless of the bank that an input change
58        occurred on. If it is not set, the interrupt are only generated for the
59        bank they belong to.
60        On devices with only one interrupt output this property is useless.
61- microchip,irq-active-high: Sets the INTPOL flag in the IOCON register. This
62        configures the IRQ output polarity as active high.
63
64Example I2C (with interrupt):
65gpiom1: gpio@20 {
66        compatible = "microchip,mcp23017";
67        gpio-controller;
68        #gpio-cells = <2>;
69        reg = <0x20>;
70
71        interrupt-parent = <&gpio1>;
72        interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
73        interrupt-controller;
74        #interrupt-cells=<2>;
75        microchip,irq-mirror;
76};
77
78Example SPI:
79gpiom1: gpio@0 {
80        compatible = "microchip,mcp23s17";
81        gpio-controller;
82        #gpio-cells = <2>;
83        spi-present-mask = <0x01>;
84        reg = <0>;
85        spi-max-frequency = <1000000>;
86};
87
88Pull-up configuration
89=====================
90
91If pins are used as output, they can also be configured with pull-ups. This is
92done with pinctrl.
93
94Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
95for details of the common pinctrl bindings used by client devices,
96including the meaning of the phrase "pin configuration node".
97
98Optional Pinmux properties:
99--------------------------
100Following properties are required if default setting of pins are required
101at boot.
102- pinctrl-names: A pinctrl state named per <pinctrl-binding.txt>.
103- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
104		<pinctrl-binding.txt>.
105
106The pin configurations are defined as child of the pinctrl states node. Each
107sub-node have following properties:
108
109Required properties:
110------------------
111- pins: List of pins. Valid values of pins properties are:
112		      gpio0 ... gpio7 for the devices with 8 GPIO pins and
113		      gpio0 ... gpio15 for the devices with 16 GPIO pins.
114
115Optional properties:
116-------------------
117The following optional property is defined in the pinmux DT binding document
118<pinctrl-bindings.txt>. Absence of this property will leave the configuration
119in its default state.
120	bias-pull-up
121
122Example with pinctrl to pull-up output pins:
123gpio21: gpio@21 {
124	compatible = "microchip,mcp23017";
125	gpio-controller;
126	#gpio-cells = <0x2>;
127	reg = <0x21>;
128	interrupt-parent = <&socgpio>;
129	interrupts = <0x17 0x8>;
130	interrupt-names = "mcp23017@21 irq";
131	interrupt-controller;
132	#interrupt-cells = <0x2>;
133	microchip,irq-mirror;
134	pinctrl-names = "default";
135	pinctrl-0 = <&i2cgpio0irq &gpio21pullups>;
136
137	gpio21pullups: pinmux {
138		pins =	"gpio0", "gpio1", "gpio2", "gpio3",
139			"gpio4", "gpio5", "gpio6", "gpio7",
140			"gpio8", "gpio9", "gpio10", "gpio11",
141			"gpio12", "gpio13", "gpio14", "gpio15";
142		bias-pull-up;
143	};
144};
145