1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra124-pinmux.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra124 Pinmux Controller
8
9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12
13description: The Tegra124 pinctrl binding is very similar to the Tegra20 and
14  Tegra30 pinctrl binding, as described in nvidia,tegra20-pinmux.yaml and
15  nvidia,tegra30-pinmux.yaml. In fact, this document assumes that binding as a
16  baseline, and only documents the differences between the two bindings.
17
18properties:
19  compatible:
20    oneOf:
21      - const: nvidia,tegra124-pinmux
22      - items:
23          - const: nvidia,tegra132-pinmux
24          - const: nvidia,tegra124-pinmux
25
26  reg:
27    items:
28      - description: driver strength and pad control registers
29      - description: pinmux registers
30      - description: MIPI_PAD_CTRL registers
31
32patternProperties:
33  "^pinmux(-[a-z0-9-_]+)?$":
34    type: object
35    properties:
36      phandle: true
37
38    # pin groups
39    additionalProperties:
40      $ref: nvidia,tegra-pinmux-common.yaml
41      additionalProperties: false
42      properties:
43        nvidia,pins:
44          $ref: /schemas/types.yaml#/definitions/string-array
45          items:
46            enum: [ ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3,
47                    ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
48                    ulpi_data6_po7, ulpi_data7_po0, ulpi_clk_py0, ulpi_dir_py1,
49                    ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0, dap3_din_pp1,
50                    dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
51                    sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5,
52                    sdmmc1_dat1_py6, sdmmc1_dat0_py7, clk2_out_pw5,
53                    clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4, ddc_sda_pv5,
54                    uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6,
55                    uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7,
56                    uart3_cts_n_pa1, uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4,
57                    pu5, pu6, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5, dap4_fs_pp4,
58                    dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, clk3_out_pee0,
59                    clk3_req_pee1, pc7, pi5, pi7, pk0, pk1, pj0, pj2, pk3, pk4,
60                    pk2, pi3, pi6, pg0, pg1, pg2, pg3, pg4, pg5, pg6, pg7, ph0,
61                    ph1, ph2, ph3, ph4, ph5, ph6, ph7, pj7, pb0, pb1, pk7, pi0,
62                    pi1, pi2, pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
63                    sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0,
64                    sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3,
65                    sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6,
66                    sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0,
67                    cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6,
68                    pbb7, pcc2, jtag_rtck, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7,
69                    kb_row0_pr0, kb_row1_pr1, kb_row2_pr2, kb_row3_pr3,
70                    kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
71                    kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3,
72                    kb_row12_ps4, kb_row13_ps5, kb_row14_ps6, kb_row15_ps7,
73                    kb_col0_pq0, kb_col1_pq1, kb_col2_pq2, kb_col3_pq3,
74                    kb_col4_pq4, kb_col5_pq5, kb_col6_pq6, kb_col7_pq7,
75                    clk_32k_out_pa0, core_pwr_req, cpu_pwr_req, pwr_int_n,
76                    clk_32k_in, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2,
77                    dap1_sclk_pn3, dap_mclk1_req_pee2, dap_mclk1_pw4,
78                    spdif_in_pk6, spdif_out_pk5, dap2_fs_pa2, dap2_din_pa4,
79                    dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0,
80                    gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2,
81                    gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6,
82                    gpio_x7_aud_px7, sdmmc3_clk_pa6, sdmmc3_cmd_pa7,
83                    sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5,
84                    sdmmc3_dat3_pb4, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2,
85                    pex_wake_n_pdd3, pex_l1_rst_n_pdd5, pex_l1_clkreq_n_pdd6,
86                    hdmi_cec_pee3, sdmmc1_wp_n_pv3, sdmmc3_cd_n_pv2,
87                    gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4,
88                    usb_vbus_en1_pn5, sdmmc3_clk_lb_out_pee4,
89                    sdmmc3_clk_lb_in_pee5, gmi_clk_lb, reset_out_n,
90                    kb_row16_pt0, kb_row17_pt1, usb_vbus_en2_pff1, pff2,
91                    dp_hpd_pff0,
92                    # drive groups
93                    drive_ao1, drive_ao2, drive_at1, drive_at2, drive_at3,
94                    drive_at4, drive_at5, drive_cdev1, drive_cdev2, drive_dap1,
95                    drive_dap2, drive_dap3, drive_dap4, drive_dbg, drive_sdio3,
96                    drive_spi, drive_uaa, drive_uab, drive_uart2, drive_uart3,
97                    drive_sdio1, drive_ddc, drive_gma, drive_gme, drive_gmf,
98                    drive_gmg, drive_gmh, drive_owr, drive_uda, drive_gpv,
99                    drive_dev3, drive_cec, drive_usb_vbus_en, drive_ao3,
100                    drive_ao0, drive_hv0, drive_sdio4, drive_ao4,
101                    # MIPI pad control groups
102                    mipi_pad_ctrl_dsi_b ]
103
104        nvidia,function:
105          enum: [ blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3,
106                  displaya, displaya_alt, displayb, dtv, extperiph1,
107                  extperiph2, extperiph3, gmi, gmi_alt, hda, hsi, i2c1, i2c2,
108                  i2c3, i2c4, i2cpwr, i2s0, i2s1, i2s2, i2s3, i2s4, irda, kbc,
109                  owr, pmi, pwm0, pwm1, pwm2, pwm3, pwron, reset_out_n, rsvd1,
110                  rsvd2, rsvd3, rsvd4, sdmmc1, sdmmc2, sdmmc3, sdmmc4, soc,
111                  spdif, spi1, spi2, spi3, spi4, spi5, spi6, trace, uarta,
112                  uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5,
113                  vgp6, vi, vi_alt1, vi_alt3, vimclk2, vimclk2_alt, sata, ccla,
114                  pe0, pe, pe1, dp, rtck, sys, clk, tmds, csi, dsi_b ]
115
116        nvidia,pull: true
117        nvidia,tristate: true
118        nvidia,schmitt: true
119        nvidia,pull-down-strength: true
120        nvidia,pull-up-strength: true
121        nvidia,high-speed-mode: true
122        nvidia,low-power-mode: true
123        nvidia,enable-input: true
124        nvidia,open-drain: true
125        nvidia,lock: true
126        nvidia,io-reset: true
127        nvidia,rcv-sel: true
128        nvidia,drive-type: true
129        nvidia,slew-rate-rising: true
130        nvidia,slew-rate-falling: true
131
132      required:
133        - nvidia,pins
134
135additionalProperties: false
136
137required:
138  - compatible
139  - reg
140
141examples:
142  - |
143    #include <dt-bindings/clock/tegra124-car.h>
144    #include <dt-bindings/interrupt-controller/arm-gic.h>
145    #include <dt-bindings/pinctrl/pinctrl-tegra.h>
146
147    pinmux@70000868 {
148        compatible = "nvidia,tegra124-pinmux";
149        reg = <0x70000868 0x164>, /* Pad control registers */
150              <0x70003000 0x434>, /* Mux registers */
151              <0x70000820 0x8>;   /* MIPI pad control */
152
153        sdmmc4_default: pinmux {
154            sdmmc4_clk_pcc4 {
155                nvidia,pins = "sdmmc4_clk_pcc4";
156                nvidia,function = "sdmmc4";
157                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
158                nvidia,tristate = <TEGRA_PIN_DISABLE>;
159            };
160
161            sdmmc4_dat0_paa0 {
162                nvidia,pins = "sdmmc4_dat0_paa0",
163                              "sdmmc4_dat1_paa1",
164                              "sdmmc4_dat2_paa2",
165                              "sdmmc4_dat3_paa3",
166                              "sdmmc4_dat4_paa4",
167                              "sdmmc4_dat5_paa5",
168                              "sdmmc4_dat6_paa6",
169                              "sdmmc4_dat7_paa7";
170                nvidia,function = "sdmmc4";
171                nvidia,pull = <TEGRA_PIN_PULL_UP>;
172                nvidia,tristate = <TEGRA_PIN_DISABLE>;
173            };
174        };
175    };
176...
177