1*1f8f3bf0SThierry Reding# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2de1835e3SThierry Reding%YAML 1.2 3de1835e3SThierry Reding--- 4de1835e3SThierry Reding$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra194-pinmux.yaml# 5de1835e3SThierry Reding$schema: http://devicetree.org/meta-schemas/core.yaml# 6de1835e3SThierry Reding 7de1835e3SThierry Redingtitle: NVIDIA Tegra194 Pinmux Controller 8de1835e3SThierry Reding 9de1835e3SThierry Redingmaintainers: 10de1835e3SThierry Reding - Thierry Reding <thierry.reding@gmail.com> 11de1835e3SThierry Reding - Jon Hunter <jonathanh@nvidia.com> 12de1835e3SThierry Reding 13de1835e3SThierry Redingproperties: 14de1835e3SThierry Reding compatible: 15*1f8f3bf0SThierry Reding enum: 16*1f8f3bf0SThierry Reding - nvidia,tegra194-pinmux 17*1f8f3bf0SThierry Reding - nvidia,tegra194-pinmux-aon 18de1835e3SThierry Reding 19de1835e3SThierry Reding reg: 20de1835e3SThierry Reding items: 21*1f8f3bf0SThierry Reding - description: pinmux registers 22de1835e3SThierry Reding 23de1835e3SThierry RedingpatternProperties: 24de1835e3SThierry Reding "^pinmux(-[a-z0-9-_]+)?$": 25de1835e3SThierry Reding type: object 26de1835e3SThierry Reding properties: 27de1835e3SThierry Reding phandle: true 28de1835e3SThierry Reding 29de1835e3SThierry Reding # pin groups 30de1835e3SThierry Reding additionalProperties: 31de1835e3SThierry Reding $ref: nvidia,tegra-pinmux-common.yaml 32*1f8f3bf0SThierry Reding unevaluatedProperties: false 33de1835e3SThierry Reding properties: 34de1835e3SThierry Reding nvidia,function: 35*1f8f3bf0SThierry Reding enum: [ aud, can0, can1, ccla, dca, dcb, dgpu, directdc, directdc1, 36*1f8f3bf0SThierry Reding displaya, displayb, dmic1, dmic2, dmic3, dmic4, dmic5, dp, 37*1f8f3bf0SThierry Reding dspk0, dspk1, eqos, extperiph1, extperiph2, extperiph3, 38*1f8f3bf0SThierry Reding extperiph4, gp, gpio, hdmi, i2c1, i2c2, i2c3, i2c5, i2c8, 39*1f8f3bf0SThierry Reding i2s1, i2s2, i2s3, i2s4, i2s5, i2s6, igpu, iqc1, iqc2, mipi, 40*1f8f3bf0SThierry Reding nv, pe0, pe1, pe2, pe3, pe4, pe5, qspi, qspi0, qspi1, rsvd0, 41*1f8f3bf0SThierry Reding rsvd1, rsvd2, rsvd3, sata, sce, sdmmc1, sdmmc3, sdmmc4, slvs, 42*1f8f3bf0SThierry Reding soc, spdif, spi1, spi2, spi3, touch, uarta, uartb, uartc, 43*1f8f3bf0SThierry Reding uartd, uarte, uartg, ufs0, usb, vgp1, vgp2, vgp3, vgp4, vgp5, 44*1f8f3bf0SThierry Reding vgp6, wdt ] 45de1835e3SThierry Reding 46de1835e3SThierry Reding nvidia,pull: true 47de1835e3SThierry Reding nvidia,tristate: true 48de1835e3SThierry Reding nvidia,schmitt: true 49de1835e3SThierry Reding nvidia,enable-input: true 50de1835e3SThierry Reding nvidia,open-drain: true 51de1835e3SThierry Reding nvidia,lock: true 52de1835e3SThierry Reding nvidia,drive-type: true 53de1835e3SThierry Reding nvidia,io-hv: true 54de1835e3SThierry Reding 55de1835e3SThierry Reding required: 56de1835e3SThierry Reding - nvidia,pins 57de1835e3SThierry Reding 58de1835e3SThierry RedingadditionalProperties: false 59de1835e3SThierry Reding 60*1f8f3bf0SThierry RedingallOf: 61*1f8f3bf0SThierry Reding - if: 62*1f8f3bf0SThierry Reding properties: 63*1f8f3bf0SThierry Reding compatible: 64*1f8f3bf0SThierry Reding const: nvidia,tegra194-pinmux 65*1f8f3bf0SThierry Reding then: 66*1f8f3bf0SThierry Reding patternProperties: 67*1f8f3bf0SThierry Reding "^pinmux(-[a-z0-9-_]+)?$": 68*1f8f3bf0SThierry Reding type: object 69*1f8f3bf0SThierry Reding additionalProperties: 70*1f8f3bf0SThierry Reding properties: 71*1f8f3bf0SThierry Reding nvidia,pins: 72*1f8f3bf0SThierry Reding description: An array of strings. Each string contains the name 73*1f8f3bf0SThierry Reding of a pin or group. Valid values for these names are listed 74*1f8f3bf0SThierry Reding below. 75*1f8f3bf0SThierry Reding 76*1f8f3bf0SThierry Reding Note that the pex_l5_clkreq_n_pgg0 and pex_l5_rst_n_pgg1 pins 77*1f8f3bf0SThierry Reding are part of PCIE C5 power partition. Client devices must 78*1f8f3bf0SThierry Reding enable this partition before accessing the configuration for 79*1f8f3bf0SThierry Reding these pins. 80*1f8f3bf0SThierry Reding items: 81*1f8f3bf0SThierry Reding enum: [ dap6_sclk_pa0, dap6_dout_pa1, dap6_din_pa2, 82*1f8f3bf0SThierry Reding dap6_fs_pa3, dap4_sclk_pa4, dap4_dout_pa5, 83*1f8f3bf0SThierry Reding dap4_din_pa6, dap4_fs_pa7, cpu_pwr_req_0_pb0, 84*1f8f3bf0SThierry Reding cpu_pwr_req_1_pb1, qspi0_sck_pc0, qspi0_cs_n_pc1, 85*1f8f3bf0SThierry Reding qspi0_io0_pc2, qspi0_io1_pc3, qspi0_io2_pc4, 86*1f8f3bf0SThierry Reding qspi0_io3_pc5, qspi1_sck_pc6, qspi1_cs_n_pc7, 87*1f8f3bf0SThierry Reding qspi1_io0_pd0, qspi1_io1_pd1, qspi1_io2_pd2, 88*1f8f3bf0SThierry Reding qspi1_io3_pd3, eqos_txc_pe0, eqos_td0_pe1, 89*1f8f3bf0SThierry Reding eqos_td1_pe2, eqos_td2_pe3, eqos_td3_pe4, 90*1f8f3bf0SThierry Reding eqos_tx_ctl_pe5, eqos_rd0_pe6, eqos_rd1_pe7, 91*1f8f3bf0SThierry Reding eqos_rd2_pf0, eqos_rd3_pf1, eqos_rx_ctl_pf2, 92*1f8f3bf0SThierry Reding eqos_rxc_pf3, eqos_sma_mdio_pf4, eqos_sma_mdc_pf5, 93*1f8f3bf0SThierry Reding soc_gpio00_pg0, soc_gpio01_pg1, soc_gpio02_pg2, 94*1f8f3bf0SThierry Reding soc_gpio03_pg3, soc_gpio08_pg4, soc_gpio09_pg5, 95*1f8f3bf0SThierry Reding soc_gpio10_pg6, soc_gpio11_pg7, soc_gpio12_ph0, 96*1f8f3bf0SThierry Reding soc_gpio13_ph1, soc_gpio14_ph2, uart4_tx_ph3, 97*1f8f3bf0SThierry Reding uart4_rx_ph4, uart4_rts_ph5, uart4_cts_ph6, 98*1f8f3bf0SThierry Reding dap2_sclk_ph7, dap2_dout_pi0, dap2_din_pi1, 99*1f8f3bf0SThierry Reding dap2_fs_pi2, gen1_i2c_scl_pi3, gen1_i2c_sda_pi4, 100*1f8f3bf0SThierry Reding sdmmc1_clk_pj0, sdmmc1_cmd_pj1, sdmmc1_dat0_pj2, 101*1f8f3bf0SThierry Reding sdmmc1_dat1_pj3, sdmmc1_dat2_pj4, sdmmc1_dat3_pj5, 102*1f8f3bf0SThierry Reding pex_l0_clkreq_n_pk0, pex_l0_rst_n_pk1, 103*1f8f3bf0SThierry Reding pex_l1_clkreq_n_pk2, pex_l1_rst_n_pk3, 104*1f8f3bf0SThierry Reding pex_l2_clkreq_n_pk4, pex_l2_rst_n_pk5, 105*1f8f3bf0SThierry Reding pex_l3_clkreq_n_pk6, pex_l3_rst_n_pk7, 106*1f8f3bf0SThierry Reding pex_l4_clkreq_n_pl0, pex_l4_rst_n_pl1, 107*1f8f3bf0SThierry Reding pex_wake_n_pl2, sata_dev_slp_pl3, dp_aux_ch0_hpd_pm0, 108*1f8f3bf0SThierry Reding dp_aux_ch1_hpd_pm1, dp_aux_ch2_hpd_pm2, 109*1f8f3bf0SThierry Reding dp_aux_ch3_hpd_pm3, hdmi_cec_pm4, soc_gpio50_pm5, 110*1f8f3bf0SThierry Reding soc_gpio51_pm6, soc_gpio52_pm7, soc_gpio53_pn0, 111*1f8f3bf0SThierry Reding soc_gpio54_pn1, soc_gpio55_pn2, sdmmc3_clk_po0, 112*1f8f3bf0SThierry Reding sdmmc3_cmd_po1, sdmmc3_dat0_po2, sdmmc3_dat1_po3, 113*1f8f3bf0SThierry Reding sdmmc3_dat2_po4, sdmmc3_dat3_po5, extperiph1_clk_pp0, 114*1f8f3bf0SThierry Reding extperiph2_clk_pp1, cam_i2c_scl_pp2, cam_i2c_sda_pp3, 115*1f8f3bf0SThierry Reding soc_gpio04_pp4, soc_gpio05_pp5, soc_gpio06_pp6, 116*1f8f3bf0SThierry Reding soc_gpio07_pp7, soc_gpio20_pq0, soc_gpio21_pq1, 117*1f8f3bf0SThierry Reding soc_gpio22_pq2, soc_gpio23_pq3, soc_gpio40_pq4, 118*1f8f3bf0SThierry Reding soc_gpio41_pq5, soc_gpio42_pq6, soc_gpio43_pq7, 119*1f8f3bf0SThierry Reding soc_gpio44_pr0, soc_gpio45_pr1, uart1_tx_pr2, 120*1f8f3bf0SThierry Reding uart1_rx_pr3, uart1_rts_pr4, uart1_cts_pr5, 121*1f8f3bf0SThierry Reding dap1_sclk_ps0, dap1_dout_ps1, dap1_din_ps2, 122*1f8f3bf0SThierry Reding dap1_fs_ps3, aud_mclk_ps4, soc_gpio30_ps5, 123*1f8f3bf0SThierry Reding soc_gpio31_ps6, soc_gpio32_ps7, soc_gpio33_pt0, 124*1f8f3bf0SThierry Reding dap3_sclk_pt1, dap3_dout_pt2, dap3_din_pt3, 125*1f8f3bf0SThierry Reding dap3_fs_pt4, dap5_sclk_pt5, dap5_dout_pt6, 126*1f8f3bf0SThierry Reding dap5_din_pt7, dap5_fs_pu0, directdc1_clk_pv0, 127*1f8f3bf0SThierry Reding directdc1_in_pv1, directdc1_out0_pv2, 128*1f8f3bf0SThierry Reding directdc1_out1_pv3, directdc1_out2_pv4, 129*1f8f3bf0SThierry Reding directdc1_out3_pv5, directdc1_out4_pv6, 130*1f8f3bf0SThierry Reding directdc1_out5_pv7, directdc1_out6_pw0, 131*1f8f3bf0SThierry Reding directdc1_out7_pw1, gpu_pwr_req_px0, cv_pwr_req_px1, 132*1f8f3bf0SThierry Reding gp_pwm2_px2, gp_pwm3_px3, uart2_tx_px4, uart2_rx_px5, 133*1f8f3bf0SThierry Reding uart2_rts_px6, uart2_cts_px7, spi3_sck_py0, 134*1f8f3bf0SThierry Reding spi3_miso_py1, spi3_mosi_py2, spi3_cs0_py3, 135*1f8f3bf0SThierry Reding spi3_cs1_py4, uart5_tx_py5, uart5_rx_py6, 136*1f8f3bf0SThierry Reding uart5_rts_py7, uart5_cts_pz0, usb_vbus_en0_pz1, 137*1f8f3bf0SThierry Reding usb_vbus_en1_pz2, spi1_sck_pz3, spi1_miso_pz4, 138*1f8f3bf0SThierry Reding spi1_mosi_pz5, spi1_cs0_pz6, spi1_cs1_pz7, 139*1f8f3bf0SThierry Reding ufs0_ref_clk_pff0, ufs0_rst_pff1, 140*1f8f3bf0SThierry Reding pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1, 141*1f8f3bf0SThierry Reding directdc_comp, sdmmc4_clk, sdmmc4_cmd, sdmmc4_dqs, 142*1f8f3bf0SThierry Reding sdmmc4_dat7, sdmmc4_dat6, sdmmc4_dat5, sdmmc4_dat4, 143*1f8f3bf0SThierry Reding sdmmc4_dat3, sdmmc4_dat2, sdmmc4_dat1, sdmmc4_dat0, 144*1f8f3bf0SThierry Reding sdmmc1_comp, sdmmc1_hv_trim, sdmmc3_comp, 145*1f8f3bf0SThierry Reding sdmmc3_hv_trim, eqos_comp, qspi_comp, 146*1f8f3bf0SThierry Reding # drive groups 147*1f8f3bf0SThierry Reding drive_soc_gpio33_pt0, drive_soc_gpio32_ps7, 148*1f8f3bf0SThierry Reding drive_soc_gpio31_ps6, drive_soc_gpio30_ps5, 149*1f8f3bf0SThierry Reding drive_aud_mclk_ps4, drive_dap1_fs_ps3, 150*1f8f3bf0SThierry Reding drive_dap1_din_ps2, drive_dap1_dout_ps1, 151*1f8f3bf0SThierry Reding drive_dap1_sclk_ps0, drive_dap3_fs_pt4, 152*1f8f3bf0SThierry Reding drive_dap3_din_pt3, drive_dap3_dout_pt2, 153*1f8f3bf0SThierry Reding drive_dap3_sclk_pt1, drive_dap5_fs_pu0, 154*1f8f3bf0SThierry Reding drive_dap5_din_pt7, drive_dap5_dout_pt6, 155*1f8f3bf0SThierry Reding drive_dap5_sclk_pt5, drive_dap6_fs_pa3, 156*1f8f3bf0SThierry Reding drive_dap6_din_pa2, drive_dap6_dout_pa1, 157*1f8f3bf0SThierry Reding drive_dap6_sclk_pa0, drive_dap4_fs_pa7, 158*1f8f3bf0SThierry Reding drive_dap4_din_pa6, drive_dap4_dout_pa5, 159*1f8f3bf0SThierry Reding drive_dap4_sclk_pa4, drive_extperiph2_clk_pp1, 160*1f8f3bf0SThierry Reding drive_extperiph1_clk_pp0, drive_cam_i2c_sda_pp3, 161*1f8f3bf0SThierry Reding drive_cam_i2c_scl_pp2, drive_soc_gpio40_pq4, 162*1f8f3bf0SThierry Reding drive_soc_gpio41_pq5, drive_soc_gpio42_pq6, 163*1f8f3bf0SThierry Reding drive_soc_gpio43_pq7, drive_soc_gpio44_pr0, 164*1f8f3bf0SThierry Reding drive_soc_gpio45_pr1, drive_soc_gpio20_pq0, 165*1f8f3bf0SThierry Reding drive_soc_gpio21_pq1, drive_soc_gpio22_pq2, 166*1f8f3bf0SThierry Reding drive_soc_gpio23_pq3, drive_soc_gpio04_pp4, 167*1f8f3bf0SThierry Reding drive_soc_gpio05_pp5, drive_soc_gpio06_pp6, 168*1f8f3bf0SThierry Reding drive_soc_gpio07_pp7, drive_uart1_cts_pr5, 169*1f8f3bf0SThierry Reding drive_uart1_rts_pr4, drive_uart1_rx_pr3, 170*1f8f3bf0SThierry Reding drive_uart1_tx_pr2, drive_dap2_din_pi1, 171*1f8f3bf0SThierry Reding drive_dap2_dout_pi0, drive_dap2_fs_pi2, 172*1f8f3bf0SThierry Reding drive_dap2_sclk_ph7, drive_uart4_cts_ph6, 173*1f8f3bf0SThierry Reding drive_uart4_rts_ph5, drive_uart4_rx_ph4, 174*1f8f3bf0SThierry Reding drive_uart4_tx_ph3, drive_soc_gpio03_pg3, 175*1f8f3bf0SThierry Reding drive_soc_gpio02_pg2, drive_soc_gpio01_pg1, 176*1f8f3bf0SThierry Reding drive_soc_gpio00_pg0, drive_gen1_i2c_scl_pi3, 177*1f8f3bf0SThierry Reding drive_gen1_i2c_sda_pi4, drive_soc_gpio08_pg4, 178*1f8f3bf0SThierry Reding drive_soc_gpio09_pg5, drive_soc_gpio10_pg6, 179*1f8f3bf0SThierry Reding drive_soc_gpio11_pg7, drive_soc_gpio12_ph0, 180*1f8f3bf0SThierry Reding drive_soc_gpio13_ph1, drive_soc_gpio14_ph2, 181*1f8f3bf0SThierry Reding drive_soc_gpio50_pm5, drive_soc_gpio51_pm6, 182*1f8f3bf0SThierry Reding drive_soc_gpio52_pm7, drive_soc_gpio53_pn0, 183*1f8f3bf0SThierry Reding drive_soc_gpio54_pn1, drive_soc_gpio55_pn2, 184*1f8f3bf0SThierry Reding drive_dp_aux_ch0_hpd_pm0, drive_dp_aux_ch1_hpd_pm1, 185*1f8f3bf0SThierry Reding drive_dp_aux_ch2_hpd_pm2, drive_dp_aux_ch3_hpd_pm3, 186*1f8f3bf0SThierry Reding drive_hdmi_cec_pm4, drive_pex_l2_clkreq_n_pk4, 187*1f8f3bf0SThierry Reding drive_pex_wake_n_pl2, drive_pex_l1_clkreq_n_pk2, 188*1f8f3bf0SThierry Reding drive_pex_l1_rst_n_pk3, drive_pex_l0_clkreq_n_pk0, 189*1f8f3bf0SThierry Reding drive_pex_l0_rst_n_pk1, drive_pex_l2_rst_n_pk5, 190*1f8f3bf0SThierry Reding drive_pex_l3_clkreq_n_pk6, drive_pex_l3_rst_n_pk7, 191*1f8f3bf0SThierry Reding drive_pex_l4_clkreq_n_pl0, drive_pex_l4_rst_n_pl1, 192*1f8f3bf0SThierry Reding drive_sata_dev_slp_pl3, drive_pex_l5_clkreq_n_pgg0, 193*1f8f3bf0SThierry Reding drive_pex_l5_rst_n_pgg1, drive_cpu_pwr_req_1_pb1, 194*1f8f3bf0SThierry Reding drive_cpu_pwr_req_0_pb0, drive_sdmmc1_clk_pj0, 195*1f8f3bf0SThierry Reding drive_sdmmc1_cmd_pj1, drive_sdmmc1_dat3_pj5, 196*1f8f3bf0SThierry Reding drive_sdmmc1_dat2_pj4, drive_sdmmc1_dat1_pj3, 197*1f8f3bf0SThierry Reding drive_sdmmc1_dat0_pj2, drive_sdmmc3_dat3_po5, 198*1f8f3bf0SThierry Reding drive_sdmmc3_dat2_po4, drive_sdmmc3_dat1_po3, 199*1f8f3bf0SThierry Reding drive_sdmmc3_dat0_po2, drive_sdmmc3_cmd_po1, 200*1f8f3bf0SThierry Reding drive_sdmmc3_clk_po0, drive_gpu_pwr_req_px0, 201*1f8f3bf0SThierry Reding drive_spi3_miso_py1, drive_spi1_cs0_pz6, 202*1f8f3bf0SThierry Reding drive_spi3_cs0_py3, drive_spi1_miso_pz4, 203*1f8f3bf0SThierry Reding drive_spi3_cs1_py4, drive_gp_pwm3_px3, 204*1f8f3bf0SThierry Reding drive_gp_pwm2_px2, drive_spi1_sck_pz3, 205*1f8f3bf0SThierry Reding drive_spi3_sck_py0, drive_spi1_cs1_pz7, 206*1f8f3bf0SThierry Reding drive_spi1_mosi_pz5, drive_spi3_mosi_py2, 207*1f8f3bf0SThierry Reding drive_cv_pwr_req_px1, drive_uart2_tx_px4, 208*1f8f3bf0SThierry Reding drive_uart2_rx_px5, drive_uart2_rts_px6, 209*1f8f3bf0SThierry Reding drive_uart2_cts_px7, drive_uart5_rx_py6, 210*1f8f3bf0SThierry Reding drive_uart5_tx_py5, drive_uart5_rts_py7, 211*1f8f3bf0SThierry Reding drive_uart5_cts_pz0, drive_usb_vbus_en0_pz1, 212*1f8f3bf0SThierry Reding drive_usb_vbus_en1_pz2, drive_ufs0_rst_pff1, 213*1f8f3bf0SThierry Reding drive_ufs0_ref_clk_pff0 ] 214*1f8f3bf0SThierry Reding 215*1f8f3bf0SThierry Reding - if: 216*1f8f3bf0SThierry Reding properties: 217*1f8f3bf0SThierry Reding compatible: 218*1f8f3bf0SThierry Reding const: nvidia,tegra194-pinmux-aon 219*1f8f3bf0SThierry Reding then: 220*1f8f3bf0SThierry Reding patternProperties: 221*1f8f3bf0SThierry Reding "^pinmux(-[a-z0-9-_]+)?$": 222*1f8f3bf0SThierry Reding type: object 223*1f8f3bf0SThierry Reding additionalProperties: 224*1f8f3bf0SThierry Reding properties: 225*1f8f3bf0SThierry Reding nvidia,pins: 226*1f8f3bf0SThierry Reding items: 227*1f8f3bf0SThierry Reding enum: [ can1_dout_paa0, can1_din_paa1, can0_dout_paa2, 228*1f8f3bf0SThierry Reding can0_din_paa3, can0_stb_paa4, can0_en_paa5, 229*1f8f3bf0SThierry Reding can0_wake_paa6, can0_err_paa7, can1_stb_pbb0, 230*1f8f3bf0SThierry Reding can1_en_pbb1, can1_wake_pbb2, can1_err_pbb3, 231*1f8f3bf0SThierry Reding spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2, 232*1f8f3bf0SThierry Reding spi2_cs0_pcc3, touch_clk_pcc4, uart3_tx_pcc5, 233*1f8f3bf0SThierry Reding uart3_rx_pcc6, gen2_i2c_scl_pcc7, gen2_i2c_sda_pdd0, 234*1f8f3bf0SThierry Reding gen8_i2c_scl_pdd1, gen8_i2c_sda_pdd2, 235*1f8f3bf0SThierry Reding safe_state_pee0, vcomp_alert_pee1, 236*1f8f3bf0SThierry Reding ao_retention_n_pee2, batt_oc_pee3, power_on_pee4, 237*1f8f3bf0SThierry Reding pwr_i2c_scl_pee5, pwr_i2c_sda_pee6, sys_reset_n, 238*1f8f3bf0SThierry Reding shutdown_n, pmu_int_n, soc_pwr_req, clk_32k_in, 239*1f8f3bf0SThierry Reding # drive groups 240*1f8f3bf0SThierry Reding drive_shutdown_n, drive_pmu_int_n, 241*1f8f3bf0SThierry Reding drive_safe_state_pee0, drive_vcomp_alert_pee1, 242*1f8f3bf0SThierry Reding drive_soc_pwr_req, drive_batt_oc_pee3, 243*1f8f3bf0SThierry Reding drive_clk_32k_in, drive_power_on_pee4, 244*1f8f3bf0SThierry Reding drive_pwr_i2c_scl_pee5, drive_pwr_i2c_sda_pee6, 245*1f8f3bf0SThierry Reding drive_ao_retention_n_pee2, drive_touch_clk_pcc4, 246*1f8f3bf0SThierry Reding drive_uart3_rx_pcc6, drive_uart3_tx_pcc5, 247*1f8f3bf0SThierry Reding drive_gen8_i2c_sda_pdd2, drive_gen8_i2c_scl_pdd1, 248*1f8f3bf0SThierry Reding drive_spi2_mosi_pcc2, drive_gen2_i2c_scl_pcc7, 249*1f8f3bf0SThierry Reding drive_spi2_cs0_pcc3, drive_gen2_i2c_sda_pdd0, 250*1f8f3bf0SThierry Reding drive_spi2_sck_pcc0, drive_spi2_miso_pcc1, 251*1f8f3bf0SThierry Reding drive_can1_dout_paa0, drive_can1_din_paa1, 252*1f8f3bf0SThierry Reding drive_can0_dout_paa2, drive_can0_din_paa3, 253*1f8f3bf0SThierry Reding drive_can0_stb_paa4, drive_can0_en_paa5, 254*1f8f3bf0SThierry Reding drive_can0_wake_paa6, drive_can0_err_paa7, 255*1f8f3bf0SThierry Reding drive_can1_stb_pbb0, drive_can1_en_pbb1, 256*1f8f3bf0SThierry Reding drive_can1_wake_pbb2, drive_can1_err_pbb3 ] 257*1f8f3bf0SThierry Reding 258de1835e3SThierry Redingrequired: 259de1835e3SThierry Reding - compatible 260de1835e3SThierry Reding - reg 261de1835e3SThierry Reding 262de1835e3SThierry Redingexamples: 263de1835e3SThierry Reding - | 264de1835e3SThierry Reding #include <dt-bindings/pinctrl/pinctrl-tegra.h> 265de1835e3SThierry Reding 266de1835e3SThierry Reding pinmux@2430000 { 267de1835e3SThierry Reding compatible = "nvidia,tegra194-pinmux"; 268*1f8f3bf0SThierry Reding reg = <0x2430000 0x17000>; 269de1835e3SThierry Reding 270de1835e3SThierry Reding pinctrl-names = "pex_rst"; 271de1835e3SThierry Reding pinctrl-0 = <&pex_rst_c5_out_state>; 272de1835e3SThierry Reding 273de1835e3SThierry Reding pex_rst_c5_out_state: pinmux-pex-rst-c5-out { 274de1835e3SThierry Reding pex_rst { 275de1835e3SThierry Reding nvidia,pins = "pex_l5_rst_n_pgg1"; 276de1835e3SThierry Reding nvidia,schmitt = <TEGRA_PIN_DISABLE>; 277de1835e3SThierry Reding nvidia,enable-input = <TEGRA_PIN_DISABLE>; 278de1835e3SThierry Reding nvidia,io-hv = <TEGRA_PIN_ENABLE>; 279de1835e3SThierry Reding nvidia,tristate = <TEGRA_PIN_DISABLE>; 280de1835e3SThierry Reding nvidia,pull = <TEGRA_PIN_PULL_NONE>; 281de1835e3SThierry Reding }; 282de1835e3SThierry Reding }; 283de1835e3SThierry Reding }; 284de1835e3SThierry Reding... 285