1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/nuvoton,npcm845-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Nuvoton NPCM845 Pin Controller and GPIO
8
9maintainers:
10  - Tomer Maimon <tmaimon77@gmail.com>
11
12description:
13  The Nuvoton BMC NPCM8XX Pin Controller multi-function routed through
14  the multiplexing block, Each pin supports GPIO functionality (GPIOx)
15  and multiple functions that directly connect the pin to different
16  hardware blocks.
17
18properties:
19  compatible:
20    const: nuvoton,npcm845-pinctrl
21
22  ranges:
23    maxItems: 1
24
25  '#address-cells':
26    const: 1
27
28  '#size-cells':
29    const: 1
30
31  nuvoton,sysgcr:
32    $ref: /schemas/types.yaml#/definitions/phandle
33    description: a phandle to access GCR registers.
34
35patternProperties:
36  '^gpio@':
37    type: object
38
39    description:
40      Eight GPIO banks that each contain 32 GPIOs.
41
42    properties:
43      gpio-controller: true
44
45      '#gpio-cells':
46        const: 2
47
48      reg:
49        maxItems: 1
50
51      interrupts:
52        maxItems: 1
53
54      gpio-ranges:
55        maxItems: 1
56
57    required:
58      - gpio-controller
59      - '#gpio-cells'
60      - reg
61      - interrupts
62      - gpio-ranges
63
64  '-mux$':
65    $ref: pinmux-node.yaml#
66
67    properties:
68      groups:
69        description:
70          One or more groups of pins to mux to a certain function
71        items:
72          enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi,
73                  smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b,
74                  smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21,
75                  smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3,
76                  spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2,
77                  spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2,
78                  bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen,
79                  r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3,
80                  fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,
81                  fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2,
82                  pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,
83                  ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2,
84                  smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
85                  sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
86                  mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,
87                  scipme, smi, smb6, smb7, spi1, faninx, r1, spi3, spi3cs1,
88                  spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c, smb0den,
89                  smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13, spix,
90                  spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,
91                  hgpio5, hgpio6, hgpio7 ]
92
93      function:
94        description:
95          The function that a group of pins is muxed to
96        enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi,
97                smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b,
98                smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21,
99                smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3,
100                spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2,
101                spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2,
102                bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen,
103                r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3,
104                fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,
105                fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2,
106                pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,
107                ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2,
108                smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
109                sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
110                mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,
111                scipme, smi, smb6, smb7, spi1, faninx, r1, spi3, spi3cs1,
112                spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c, smb0den,
113                smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13, spix,
114                spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,
115                hgpio5, hgpio6, hgpio7 ]
116
117    dependencies:
118      groups: [ function ]
119      function: [ groups ]
120
121    additionalProperties: false
122
123  '^pin':
124    $ref: pincfg-node.yaml#
125
126    properties:
127      pins:
128        description:
129          A list of pins to configure in certain ways, such as enabling
130          debouncing
131        items:
132          pattern: '^GPIO([0-9]|[0-9][0-9]|1[0-9][0-9]|2[0-4][0-9]|25[0-6])'
133
134      bias-disable: true
135
136      bias-pull-up: true
137
138      bias-pull-down: true
139
140      input-enable: true
141
142      output-low: true
143
144      output-high: true
145
146      drive-push-pull: true
147
148      drive-open-drain: true
149
150      input-debounce:
151        description:
152          Debouncing periods in microseconds, one period per interrupt
153          bank found in the controller
154        $ref: /schemas/types.yaml#/definitions/uint32-array
155        minItems: 1
156        maxItems: 4
157
158      slew-rate:
159        description: |
160          0: Low rate
161          1: High rate
162        $ref: /schemas/types.yaml#/definitions/uint32
163        enum: [0, 1]
164
165      drive-strength:
166        enum: [ 0, 1, 2, 4, 8, 12 ]
167
168    additionalProperties: false
169
170allOf:
171  - $ref: pinctrl.yaml#
172
173required:
174  - compatible
175  - ranges
176  - '#address-cells'
177  - '#size-cells'
178  - nuvoton,sysgcr
179
180additionalProperties: false
181
182examples:
183  - |
184    #include <dt-bindings/interrupt-controller/arm-gic.h>
185    #include <dt-bindings/gpio/gpio.h>
186
187    soc {
188      #address-cells = <2>;
189      #size-cells = <2>;
190
191      pinctrl: pinctrl@f0010000 {
192        compatible = "nuvoton,npcm845-pinctrl";
193        ranges = <0x0 0x0 0xf0010000 0x8000>;
194        #address-cells = <1>;
195        #size-cells = <1>;
196        nuvoton,sysgcr = <&gcr>;
197
198        gpio0: gpio@0 {
199          gpio-controller;
200          #gpio-cells = <2>;
201          reg = <0x0 0xb0>;
202          interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
203          gpio-ranges = <&pinctrl 0 0 32>;
204        };
205
206        fanin0_pin: fanin0-mux {
207          groups = "fanin0";
208          function = "fanin0";
209        };
210
211        pin34_slew: pin34-slew {
212          pins = "GPIO34/I3C4_SDA";
213          bias-disable;
214        };
215      };
216    };
217