1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8183-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek MT8183 Pin Controller Device Tree Bindings
8
9maintainers:
10  - Sean Wang <sean.wang@kernel.org>
11
12description: |+
13  The MediaTek's MT8183 Pin controller is used to control SoC pins.
14
15properties:
16  compatible:
17    const: mediatek,mt8183-pinctrl
18
19  reg:
20    minItems: 10
21    maxItems: 10
22
23  reg-names:
24    items:
25      - const: iocfg0
26      - const: iocfg1
27      - const: iocfg2
28      - const: iocfg3
29      - const: iocfg4
30      - const: iocfg5
31      - const: iocfg6
32      - const: iocfg7
33      - const: iocfg8
34      - const: eint
35
36  gpio-controller: true
37
38  "#gpio-cells":
39    const: 2
40    description: |
41      Number of cells in GPIO specifier. Since the generic GPIO
42      binding is used, the amount of cells must be specified as 2. See the below
43      mentioned gpio binding representation for description of particular cells.
44
45  gpio-ranges:
46    minItems: 1
47    maxItems: 5
48    description: |
49      GPIO valid number range.
50
51  interrupt-controller: true
52
53  interrupts:
54    maxItems: 1
55
56  "#interrupt-cells":
57    const: 2
58
59required:
60  - compatible
61  - reg
62  - gpio-controller
63  - "#gpio-cells"
64  - gpio-ranges
65
66patternProperties:
67  '-[0-9]+$':
68    type: object
69    additionalProperties: false
70    patternProperties:
71      'pins':
72        type: object
73        additionalProperties: false
74        description: |
75          A pinctrl node should contain at least one subnodes representing the
76          pinctrl groups available on the machine. Each subnode will list the
77          pins it needs, and how they should be configured, with regard to muxer
78          configuration, pullups, drive strength, input enable/disable and input
79          schmitt.
80        $ref: "/schemas/pinctrl/pincfg-node.yaml"
81
82        properties:
83          pinmux:
84            description:
85              integer array, represents gpio pin number and mux setting.
86              Supported pin number and mux varies for different SoCs, and are
87              defined as macros in <soc>-pinfunc.h directly.
88
89          bias-disable: true
90
91          bias-pull-up: true
92
93          bias-pull-down: true
94
95          input-enable: true
96
97          input-disable: true
98
99          output-low: true
100
101          output-high: true
102
103          input-schmitt-enable: true
104
105          input-schmitt-disable: true
106
107          drive-strength:
108            enum: [2, 4, 6, 8, 10, 12, 14, 16]
109
110          mediatek,drive-strength-adv:
111            description: |
112              Describe the specific driving setup property.
113              For I2C pins, the existing generic driving setup can only support
114              2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
115              can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
116              driving setup, the existing generic setup will be disabled.
117              The specific driving setup is controlled by E1E0EN.
118              When E1=0/E0=0, the strength is 0.125mA.
119              When E1=0/E0=1, the strength is 0.25mA.
120              When E1=1/E0=0, the strength is 0.5mA.
121              When E1=1/E0=1, the strength is 1mA.
122              EN is used to enable or disable the specific driving setup.
123              Valid arguments are described as below:
124              0: (E1, E0, EN) = (0, 0, 0)
125              1: (E1, E0, EN) = (0, 0, 1)
126              2: (E1, E0, EN) = (0, 1, 0)
127              3: (E1, E0, EN) = (0, 1, 1)
128              4: (E1, E0, EN) = (1, 0, 0)
129              5: (E1, E0, EN) = (1, 0, 1)
130              6: (E1, E0, EN) = (1, 1, 0)
131              7: (E1, E0, EN) = (1, 1, 1)
132              So the valid arguments are from 0 to 7.
133            $ref: /schemas/types.yaml#/definitions/uint32
134            enum: [0, 1, 2, 3, 4, 5, 6, 7]
135
136          mediatek,pull-up-adv:
137            description: |
138              Pull up setings for 2 pull resistors, R0 and R1. User can
139              configure those special pins. Valid arguments are described as below:
140              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
141              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
142              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
143              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
144            $ref: /schemas/types.yaml#/definitions/uint32
145            enum: [0, 1, 2, 3]
146
147          mediatek,pull-down-adv:
148            description: |
149              Pull down settings for 2 pull resistors, R0 and R1. User can
150              configure those special pins. Valid arguments are described as below:
151              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
152              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
153              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
154              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
155            $ref: /schemas/types.yaml#/definitions/uint32
156            enum: [0, 1, 2, 3]
157
158          mediatek,tdsel:
159            description: |
160              An integer describing the steps for output level shifter duty
161              cycle when asserted (high pulse width adjustment). Valid arguments
162              are from 0 to 15.
163            $ref: /schemas/types.yaml#/definitions/uint32
164
165          mediatek,rdsel:
166            description: |
167              An integer describing the steps for input level shifter duty cycle
168              when asserted (high pulse width adjustment). Valid arguments are
169              from 0 to 63.
170            $ref: /schemas/types.yaml#/definitions/uint32
171
172        required:
173          - pinmux
174
175additionalProperties: false
176
177examples:
178  - |
179    #include <dt-bindings/interrupt-controller/irq.h>
180    #include <dt-bindings/interrupt-controller/arm-gic.h>
181    #include <dt-bindings/pinctrl/mt8183-pinfunc.h>
182
183    soc {
184        #address-cells = <2>;
185        #size-cells = <2>;
186
187        pio: pinctrl@10005000 {
188          compatible = "mediatek,mt8183-pinctrl";
189          reg = <0 0x10005000 0 0x1000>,
190                <0 0x11f20000 0 0x1000>,
191                <0 0x11e80000 0 0x1000>,
192                <0 0x11e70000 0 0x1000>,
193                <0 0x11e90000 0 0x1000>,
194                <0 0x11d30000 0 0x1000>,
195                <0 0x11d20000 0 0x1000>,
196                <0 0x11c50000 0 0x1000>,
197                <0 0x11f30000 0 0x1000>,
198                <0 0x1000b000 0 0x1000>;
199          reg-names = "iocfg0", "iocfg1", "iocfg2",
200                "iocfg3", "iocfg4", "iocfg5",
201                "iocfg6", "iocfg7", "iocfg8",
202                "eint";
203          gpio-controller;
204          #gpio-cells = <2>;
205          gpio-ranges = <&pio 0 0 192>;
206          interrupt-controller;
207          interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
208          #interrupt-cells = <2>;
209
210          i2c0_pins_a: i2c-0 {
211            pins1 {
212              pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
213                <PINMUX_GPIO49__FUNC_SDA5>;
214              mediatek,pull-up-adv = <3>;
215              mediatek,drive-strength-adv = <7>;
216            };
217          };
218
219          i2c1_pins_a: i2c-1 {
220            pins {
221              pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
222                <PINMUX_GPIO51__FUNC_SDA3>;
223              mediatek,pull-down-adv = <2>;
224              mediatek,drive-strength-adv = <4>;
225            };
226          };
227        };
228    };
229